CY7C1061AV33
DC Input Voltage [3] ............................... –0.5V to VCC + 0.5V
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND [3] ... –0.5V to +4.6V
Range
VCC
Temperature
0°C to +70°C
–40°C to +85°C
Commercial
Industrial
3.3V ± 0.3V
DC Voltage Applied to Outputs
in High-Z State [3] ...................................–0.5V to VCC + 0.5V
DC Electrical Characteristics (Over the Operating Range)
–10
–12
Parameter
Description
Test Conditions
Unit
Min
Max
Min
Max
VOH
VOL
VIH
VIL
IIX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage [3]
IOH = –4.0 mA
IOL = 8.0 mA
2.4
2.4
V
V
0.4
0.4
2.0
VCC + 0.3
0.8
2.0
–0.3
–1
VCC + 0.3
0.8
V
–0.3
–1
V
Input Leakage Current GND < VI < VCC
+1
+1
µA
µA
mA
mA
mA
IOZ
ICC
Output Leakage Current GND < VO < VCC, Output Disabled
–1
+1
–1
+1
VCC Operating
Supply Current
VCC = max,
f = fmax = 1/tRC
Commercial
Industrial
275
275
70
260
260
70
ISB1
Automatic CE
Power-down Current
—TTL Inputs
CE2 <= VIL, max VCC, CE > VIH
VIN > VIH or
V
IN < VIL, f = fmax
CE2 <= 0.3V
max VCC
ISB2
Automatic CE
Power-down Current
—CMOS Inputs
Commercial/
Industrial
50
50
mA
,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
Capacitance [4]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 3.3V
TSOP II
FBGA
8
Unit
CIN
Input Capacitance
IO Capacitance
6
8
pF
pF
COUT
10
AC Test Loads and Waveforms [5]
50Ω
R1 317
Ω
= 1.5V
OUTPUT
VTH
3.3V
Z = 50Ω
OUTPUT
30 pF* * Capacitive Load consists of all com-
ponents of the test environment.
0
R2
351Ω
5 pF*
(a)
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
3.3V
(b)
90%
10%
90%
10%
GND
Fall time:
> 1V/ns
Rise time > 1V/ns
(c)
Notes
3.
4. Tested initially and after any design or process changes that may affect these parameters.
5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V (3.0V). As soon as 1 ms (T
V
(min) = –2.0V for pulse durations of less than 20 ns.
IL
) after reaching the
power
DD
minimum operating V , normal SRAM operation can begin including reduction in V to the data retention (V , 2.0V) voltage.
CCDR
DD
DD
Document #: 38-05256 Rev. *G
Page 3 of 10
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