CY7C1061AV33
AC Switching Characteristics (Over the Operating Range) [6]
–10
–12
Parameter
Description
Unit
Min
Max
Min
Max
Read Cycle
tpower
tRC
VCC(typical) to the first access [7]
Read Cycle Time
1
1
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
12
tAA
Address to Data Valid
10
12
tOHA
tACE
Data Hold from Address Change
CE1 LOW/CE2 HIGH to Data Valid
OE LOW to Data Valid
3
3
10
5
12
6
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
OE LOW to Low-Z
OE HIGH to High-Z [8]
1
3
0
1
3
0
5
5
6
6
CE1 LOW/CE2 HIGH to Low-Z [8]
CE1 HIGH/CE2 LOW to High-Z [8]
CE1 LOW/CE2 HIGH to Power Up [9]
CE1 HIGH/CE2 LOW to Power Down [9]
Byte Enable to Data Valid
Byte Enable to Low-Z
tPD
10
5
12
6
tDBE
tLZBE
tHZBE
Write Cycle [10, 11]
tWC
1
1
Byte Disable to High-Z
5
6
Write Cycle Time
10
7
12
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCE
CE1 LOW/CE2 HIGH to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
tAW
7
8
tHA
0
0
tSA
0
0
tPWE
tSD
7
8
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low-Z [8]
5.5
0
6
tHD
0
tLZWE
tHZWE
tBW
3
3
WE LOW to High-Z [8]
5
6
Byte Enable to End of Write
7
8
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
[5]
I
/I and specified transmission line loads. Test conditions for the Read cycle use output loading shown in (a) of the “AC Test Loads and Waveforms ” on
OL OH
page 3, unless specified otherwise.
7. This part has a voltage regulator that steps down the voltage from 3V to 2V internally. t
time must be provided initially before a Read/Write operation is started.
power
[5]
8.
t
, t
, t
, t
and t
, t
, t
, t
are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms ” on page 3.
HZOE HZCE HZWE HZBE
LZOE LZCE \LZWE LZBE
Transition is measured ±200 mV from steady-state voltage.
9. These parameters are guaranteed by design and are not tested.
10. The internal Write time of the memory is defined by the overlap of CE LOW (CE HIGH) and WE LOW. Chip enables must be active and WE and byte enables
1
2
must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to
the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
and t
.
SD
HZWE
Document #: 38-05256 Rev. *G
Page 4 of 10
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