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CY7B994V-5AC 参数 Datasheet PDF下载

CY7B994V-5AC图片预览
型号: CY7B994V-5AC
PDF下载: 下载PDF文件 查看货源
内容描述: 高速多相位锁相环时钟缓冲器 [High-speed Multi-phase PLL Clock Buffer]
分类和应用: 时钟
文件页数/大小: 15 页 / 392 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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RoboClock
CY7B993V
CY7B994V
Absolute Maximum Conditions
[5]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ –40°C to + 125°C
Ambient Temperature with
Power Applied............................................ –40°C to + 125°C
Supply Voltage to Ground Potential .............. –0.5V to + 4.6V
DC Input Voltage....................................–0.3V to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 40 mA
Static Discharge Voltage........................................... > 1100V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................. > ± 200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
3.3V
±
10%
3.3V
±
10%
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
I
OZ
V
IH
Description
LVTTL HIGH Voltage QFA[0:1], [1:4]Q[A:B][0:1]
LOCK
LVTTL LOW Voltage QFA[0:1], [1:4]Q[A:B][0:1]
LOCK
High-impedance State Leakage Current
LVTTL Input HIGH
FBK[A:B]±, REF[A:B]±
REFSEL, FBSEL, FBDIS,
DIS[1:4]
V
IL
I
I
I
lH
I
lL
LVTTL Input LOW
LVTTL V
IN
>V
CC
LVTTL Input HIGH
Current
LVTTL Input LOW
Current
FBK[A:B]±, REF[A:B]±
REFSEL, FBSEL, FBDIS, DIS[1:4]
FBK[A:B]±, REF[A:B]±
FBK[A:B]±, REF[A:B]±
FBK[A:B]±, REF[A:B]±
REFSEL, FBSEL, FBDIS, DIS[1:4]
Min. < V
CC
< Max.
Min. < V
CC
< Max.
Min. < V
CC
< Max.
V
CC
= GND, V
IN
= 3.63V
V
CC
= Max., V
IN
= V
CC
V
CC
= Max., V
IN
= GND
Min. < V
CC
< Max.
Min. < V
CC
< Max.
Test Conditions
V
CC
= Min., I
OH
= –30 mA
I
OH
= –2 mA, V
CC
= Min.
V
CC
= Min., I
OL
= 30 mA
I
OL
= 2 mA, V
CC
= Min.
Min.
2.4
2.4
–100
2.0
2.0
–0.3
–0.3
–500
–500
0.87*V
CC
–50
–100
–200
–400
400
1.0
GND
0.8
Max.
0.5
0.5
100
V
CC
+ 0.3
V
CC
+ 0.3
0.8
0.8
100
500
500
0.13*V
CC
200
400
50
100
V
CC
V
CC
V
CC
– 0.4
V
CC
Unit
V
V
V
V
µA
V
V
V
V
µA
µA
µA
µA
µA
V
V
V
µA
µA
µA
µA
µA
µA
mV
V
V
V
LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK)
LVTTL Compatible Input Pins (FBKA±, FBKB±, REFA±, REFB±, FBSEL, REFSEL, FBDIS, DIS[1:4])
REFSEL, FBSEL, FBDIS, DIS[1:4] V
IN
= V
CC
Three-level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST))
V
IHH
V
IMM
V
ILL
I
IHH
I
IMM
I
ILL
Three-level Input HIGH
[6]
Three-level Input MID
[6]
Three-level Input LOW
[6]
Three-level Input
HIGH Current
Three-level Input
MID Current
Three-level Input
LOW Current
FBF0
Three-level input pins excl. FBF0 V
IN
= V
CC
/2
FBF0
Three-level input pins excl. FBF0 V
IN
= GND
FBF0
0.47*V
CC
0.53*V
CC
Three-level input pins excl. FBF0 V
IN
= V
CC
LVDIFF Input Pins (FBK[A:B]±, REF[A:B]±)
V
DIFF
V
IHHP
V
ILLP
V
COM
Input Differential Voltage
Highest Input HIGH Voltage
Lowest Input LOW Voltage
Common Mode Range (crossing voltage)
Notes:
5.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
6. These inputs are normally wired to V
CC
, GND, or left unconnected (actual threshold voltages vary as a percentage of V
CC
). Internal termination resistors hold
the unconnected inputs at V
CC
/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t
LOCK
time
before all data sheet limits are achieved.
Document #: 38-07127 Rev. *F
Page 8 of 15