RoboClock
CY7B993V
CY7B994V
Electrical Characteristics
Over the Operating Range (continued)
Parameter
I
CCI
I
CCN
Description
Internal Operating
Current
Output Current
Dissipation/Pair
[8]
CY7B993V
CY7B994V
CY7B993V
CY7B994V
V
CC
= Max.,
C
LOAD
= 25 pF,
R
LOAD
= 50Ω at V
CC
/2,
f
MAX
Test Conditions
V
CC
= Max., f
MAX[7]
Min.
–
–
–
–
Max.
250
250
40
50
Unit
mA
mA
mA
mA
Operating Current
Capacitance
Parameter
C
IN
Description
Input Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz, V
CC
= 3.3V
Min.
Max.
5
Unit
pF
Switching Characteristics
Over the Operating Range
[9, 10, 11, 12, 13]
CY7B993/4V-2
Parameter
f
in
f
out
t
SKEWPR
t
SKEWBNK
t
SKEW0
t
SKEW1
t
SKEW2
Clock Input Frequency
Clock Output Frequency
Matched-Pair Skew
[14, 15]
Intrabank Skew
[14, 15]
Output-Output Skew (same frequency and phase, rise to
rise, fall to fall)
[14, 15]
Output-Output Skew (same frequency and phase, other
banks at different frequency, rise to rise, fall to fall)
[14, 15]
Output-Output Skew (invert to nominal of different banks,
compared banks at same frequency, rising edge to falling
edge aligned, other banks at same frequency)
[14, 15]
Output-Output Skew (all output configurations outside of
t
SKEW1
and t
SKEW2
)
[14, 15]
Complementary Outputs Skew (crossing to crossing,
complementary outputs of the same bank)
[14, 15, 16, 17]
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 1, 2, 3)
Cycle-to-Cycle Jitter (divide by 1 output frequency,
FB = divide by 4, 5, 6, 8, 10, 12)
Propagation Delay, REF to FB Rise
Description
CY7B993V
CY7B994V
CY7B993V
CY7B994V
Min.
12
24
12
24
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
–
–
Max.
100
200
100
200
200
200
250
250
250
CY7B993/4V-5
Min.
12
24
12
24
–
–
–
–
–
Typ.
–
–
–
–
–
–
–
–
–
Max.
100
200
100
200
200
250
550
650
700
Unit
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
t
SKEW3
t
SKEWCPR
t
CCJ1-3
t
CCJ4-12
t
PD
–
–
–
–
–250
–
–
50
50
–
500
200
150
100
250
–
–
–
–
–500
–
–
50
50
–
800
300
150
100
500
ps
ps
ps Peak
ps Peak
ps
Notes:
7. I
CCI
measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (f
NOM
= 100 MHz for CY7B993V, f
NOM
= 200 MHz for
CY7B994V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state.
8. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum I
CCN
at maximum frequency and maximum
load of 25 pF terminated to 50Ω at V
CC
/2.
9. This is for non-three level inputs.
10. Assumes 25-pF max. load capacitance up to 185 MHz. At 200 MHz the max. load is 10 pF.
11. Both outputs of pair must be terminated, even if only one is being used.
12. Each package must be properly decoupled.
13. AC parameters are measured at 1.5V unless otherwise indicated.
14. Test Load C
L
= 25 pF, terminated to V
CC
/2 with 50Ω up to185 MHz and 10-pF load to 200 MHz.
15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when
all outputs are loaded with 25 pF and properly terminated up to 185 MHz. At 200 MHz the max load is 10 pF.
16. Complementary output skews are measured at complementary signal pair intersections.
17. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-07127 Rev. *F
Page 9 of 15
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