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CY7B994V-5AC 参数 Datasheet PDF下载

CY7B994V-5AC图片预览
型号: CY7B994V-5AC
PDF下载: 下载PDF文件 查看货源
内容描述: 高速多相位锁相环时钟缓冲器 [High-speed Multi-phase PLL Clock Buffer]
分类和应用: 时钟
文件页数/大小: 15 页 / 392 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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RoboClock
CY7B993V
CY7B994V
U
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FBInput
REFInput
1F[1:0]
2F[1:0]
(N/A)
(N/A)
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
3F[1:0]
4F[1:0]
LL
LM
LH
(N/A)
(N/A)
(N/A)
(N/A)
MM
(N/A)
(N/A)
(N/A)
(N/A)
HL
HM
HH
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0t
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Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
[4]
Output Disable Description
The feedback Divide and Phase Select Matrix Bank has two
outputs, and each of the four Divide and Phase Select Matrix
Banks have four outputs. The outputs of each bank can be
independently put into a HOLD-OFF or high-impedance state.
The combination of the OUTPUT_MODE and DIS[1:4]/FBDIS
inputs determines the clock outputs’ state for each bank. When
the DIS[1:4]/FBDIS is LOW, the outputs of the corresponding
bank will be enabled. When the DIS[1:4]/FBDIS is HIGH, the
outputs for that bank will be disabled to a high-impedance
(HI-Z) or HOLD-OFF state depending on the OUTPUT_MODE
input.
Table 5
defines the disabled output functions.
The HOLD-OFF state is intended to be a power saving feature.
An output bank is disabled to the HOLD-OFF state in a
maximum of six output clock cycles from the time when the
disable input (DIS[1:4]/FBDIS) is HIGH. When disabled to the
Note:
4. FB connected to an output selected for “Zero” skew (i.e., FBF0 = MID or XF[1:0] = MID).
HOLD-OFF state, non-inverting outputs are driven to a logic
LOW state on its falling edge. Inverting outputs are driven to a
logic HIGH state on its rising edge. This ensures the output
clocks are stopped without glitch. When a bank of outputs is
disabled to HI-Z state, the respective bank of outputs will go
HI-Z immediately.
Table 5. DIS[1:4]/FBDIS Pin Functionality
OUTPUT_MODE
HIGH/LOW
HIGH
LOW
MID
DIS[1:4]/FBDIS
LOW
HIGH
HIGH
X
Output Mode
ENABLED
HI-Z
HOLD-OFF
FACTORY TEST
Document #: 38-07127 Rev. *F
Page 6 of 15
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