RoboClock
CY7B993V
CY7B994V
Switching Characteristics
Over the Operating Range
[9, 10, 11, 12, 13]
(continued)
CY7B993/4V-2
Parameter
TTB
t
PDDELTA
t
REFpwh
t
REFpwl
t
r
/t
f
t
LOCK
t
RELOCK1
t
RELOCK2
t
ODCV
t
PWH
t
PWL
t
PDEV
t
OAZ
t
OAZ
18]
CY7B993/4V-5
Min.
–
–
2.0
2.0
0.15
–
–
–
–1.0
–
–
–
1.0
0.5
Typ.
–
–
–
–
–
–
Max.
700
200
–
–
2.0
10
500
1000
1.0
1.5
2.0
0.025
10
14
Unit
ps
ps
ns
ns
ns
ms
µs
µs
ns
ns
ns
UI
ns
ns
Description
Total Timing Budget window (same frequency and phase)
[17,
Min.
–
–
2.0
2.0
0.15
–
–
–
–1.0
–
–
–
1.0
0.5
Typ.
–
–
–
–
–
–
Max.
500
200
–
–
2.0
10
500
1000
1.0
1.5
2.0
0.025
10
14
Propagation Delay difference between two devices
[17]
REF input (Pulse Width HIGH)
[19]
REF input (Pulse Width LOW)
[19]
Output Rise/Fall Time
[20]
PLL Lock Time From Power-up
PLL Relock Time (from same frequency, different phase)
with Stable Power Supply
PLL Relock Time (from different frequency, different phase)
with Stable Power Supply
[21]
Output duty cycle deviation from 50%
[13]
Output HIGH time deviation from 50%
[22]
Output LOW time deviation from 50%
[22]
Period deviation when changing from reference to
reference
[23]
DIS[1:4]/FBDIS HIGH to output high-impedance from
ACTIVE
[14, 24]
DIS[1:4]/FBDIS LOW to output ACTIVE from output
high-impedance
[24, 25]
AC Test Loads and Waveform
[26]
3.3V
For LOCK output only
R1 = 910Ω
R2 = 910Ω
C
L
< 30 pF
OUTPUT
For all other outputs
R1 = 100Ω
C
L
R2 = 100Ω
C
L
< 25 pF to 185 MHz
or 10 pF at 200 MHz
(Includes fixture and
probe capacitance)
R1
R2
(a) LVTTL AC Test Load
3.3V
GND
< 1 ns
2.0V
0.8V
2.0V
0.8V
< 1 ns
(b) TTL Input Test Waveform
Notes:
18. TTB is the window between the earliest and the latest output clocks with respect to the input reference clock across variations in output frequency, supply voltage,
operating temperature, input clock edge rate, and process. The measurements are taken with the AC test load specified and include output-output skew, cycle-cycle
jitter, and dynamic phase error. TTB will be equal to or smaller than the maximum specified value at a given frequency.
19. Tested initially and after any design or process changes that may affect these parameters.
20. Rise and fall times are measured between 2.0V and 0.8V.
21. f
NOM
must be within the frequency range defined by the same FS state.
22. t
PWH
is measured at 2.0V. t
PWL
is measured at 0.8V.
23. UI = Unit Interval. Examples: 1 UI is a full period. 0.1UI is 10% of period.
24. Measured at 0.5V deviation from starting voltage.
25. For t
OZA
minimum, C
L
= 0 pF. For t
OZA
maximum, C
L
= 25 pF to 185 MHz or 10 pF to 200 MHz.
26. These figures are for illustrations only. The actual ATE loads may vary.
Document #: 38-07127 Rev. *F
Page 10 of 15
CYPRESS [ CYPRESS SEMICONDUCTOR ]
