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CY7B991V-7JC 参数 Datasheet PDF下载

CY7B991V-7JC图片预览
型号: CY7B991V-7JC
PDF下载: 下载PDF文件 查看货源
内容描述: 低电压可编程偏移时钟缓冲器 [Low Voltage Programmable Skew Clock Buffer]
分类和应用: 时钟驱动器逻辑集成电路
文件页数/大小: 14 页 / 383 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7B991V
3.3V RoboClock
®
Switching Characteristics – 5 Option
Over the Operating Range
Parameter
f
NOM
Description
Operating Clock Frequency in MHz
FS = LOW
FS = MID
FS = HIGH
CY7B991V–5
Min
Typ
Max
15
30
25
50
40
80
5.0
5.0
See
0.1
0.25
0.25
0.5
0.6
0.7
0.5
1.0
0.5
0.7
0.5
1.0
1.25
–0.5
0.0
+0.5
–1.0
0.0
+1.0
2.5
3
0.15
1.0
1.5
0.15
1.0
1.5
0.5
25
200
Unit
MHz
t
RPWH
t
RPWL
t
U
t
SKEWPR
t
SKEW0
t
SKEW1
t
SKEW2
t
SKEW3
t
SKEW4
t
DEV
t
PD
t
ODCV
t
PWH
t
PWL
t
ORISE
t
OFALL
t
LOCK
t
JR
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched-Pair Skew (XQ0, XQ1)
Zero Output Skew (All Outputs)
Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)
Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)
Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)
Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)
Device-to-Device Skew
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation
Output HIGH Time Deviation from 50%
Output LOW Time Deviation from 50%
Output Rise Time
Output Fall Time
PLL Lock Time
Cycle-to-Cycle Output Jitter
RMS
Peak-to-Peak
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
ps
Notes
11. Test measurement levels for the CY7B991V are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown
in the AC Test Loads and Waveforms unless otherwise specified.
12. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
13. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same t
U
delay has been selected when all are
loaded with 30 pF and terminated with 50Ω to V
CC
/2 (CY7B991V).
14. t
SKEWPR
is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0t
U
.
15. t
SKEW0
is defined as the skew between outputs when they are selected for 0t
U
. Other outputs are divided or inverted but not shifted.
16. C
L
=0 pF. For C
L
=30 pF, t
SKEW0
=0.35 ns.
17. There are three classes of outputs: Nominal (multiple of t
U
delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2
or Divide-by-4 mode).
18. t
DEV
is the output-to-output skew between any two devices operating under the same conditions (V
CC
ambient temperature, air flow, etc.)
19. t
ODCV
is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
SKEW2
and t
SKEW4
specifications.
20. Specified with outputs loaded with 30 pF for the CY7B991V–5 and –7 devices. Devices are terminated through 50Ω to V
CC
/2.t
PWH
is measured at 2.0V. t
PWL
is
measured at 0.8V.
21. t
ORISE
and t
OFALL
measured between 0.8V and 2.0V.
22. t
LOCK
is the time that is required before synchronization is achieved. This specification is valid only after V
CC
is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until t
PD
is within specified limits.
Document Number: 38-07141 Rev. *C
Page 11 of 14