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CY7B991V-7JC 参数 Datasheet PDF下载

CY7B991V-7JC图片预览
型号: CY7B991V-7JC
PDF下载: 下载PDF文件 查看货源
内容描述: 低电压可编程偏移时钟缓冲器 [Low Voltage Programmable Skew Clock Buffer]
分类和应用: 时钟驱动器逻辑集成电路
文件页数/大小: 14 页 / 383 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7B991V
3.3V RoboClock
®
Electrical Characteristics
Over the Operating Range
Parameter
V
OH
V
OL
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IH
I
IL
I
IHH
I
IMM
I
ILL
I
OS
I
CCQ
I
CCN
PD
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
(REF and FB inputs only)
Input LOW Voltage
(REF and FB inputs only)
Three Level Input HIGH
Voltage (Test, FS, xFn)
Three Level Input MID
Voltage (Test, FS, xFn)
Three Level Input LOW
Voltage (Test, FS, xFn)
Min
V
CC
Max.
Min
V
CC
Max.
Min
V
CC
Max.
Test Conditions
V
CC
= Min, I
OH
= –12 mA
V
CC
= Min, I
OL
= 35 mA
2.0
–0.5
0.87 * V
CC
0.47 * V
CC
0.0
CY7B991V
Min
2.4
0.45
V
CC
0.8
V
CC
0.53 * V
CC
0.13 * V
CC
20
–20
200
–50
50
–200
–200
95
100
19
104
mA
mW
Com’l
Mil/Ind
Max
Unit
V
V
V
V
V
V
V
μA
μA
μA
μA
μA
mA
mA
Input HIGH Leakage Current (REF V
CC
= Max, V
IN
= Max.
and FB inputs only)
Input LOW Leakage Current (REF V
CC
= Max, V
IN
= 0.4V
and FB inputs only)
Input HIGH Current (Test, FS, xFn) V
IN
= V
CC
Input MID Current (Test, FS, xFn)
Short Circuit Current
V
IN
= V
CC
/2
V
CC
= MAx V
OUT
=GND (25° only)
Input LOW Current (Test, FS, xFn) V
IN
= GND
Operating Current Used by Internal V
CCN
= V
CCQ
= Max, All
Circuitry
Input Selects Open
Output Buffer Current per Output
Pair
Power Dissipation per Output
Pair
V
CCN
= V
CCQ
= Max, I
OUT
= 0 mA
Input Selects Open, f
MAX
V
CCN
= V
CCQ
= Max, I
OUT
= 0 mA
Input Selects Open, f
MAX
Notes
5. See the last page of this specification for Group A subgroup testing information.
6. These inputs are normally wired to V
CC
, GND, or left unconnected (actual threshold voltages vary as a percentage of V
CC
). Internal termination resistors hold
unconnected inputs at V
CC
/2. If these inputs are switched, the function and timing of the outputs glitch and the PLL requires an additional t
LOCK
time before all
datasheet limits are achieved.
7. CY7B991V is tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only.
8. Total output current per output pair is approximated by the following expression that includes device current plus load current:
CY7B991V: I
CCN
= [(4 + 0.11F) + [((835 –3F)/Z) + (.0022FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F
<
C
9. These inputs are normally wired to V
CC
, GND, or left unconnected (actual threshold voltages vary as a percentage of V
CC
). Internal termination resistors hold
unconnected inputs at V
CC
/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t
LOCK
time
before all datasheet limits are achieved.
Document Number: 38-07141 Rev. *C
Page 9 of 14