CY7B923
CY7B933
Capacitance
[7]
Parameter
C
IN
Description
Input Capacitance
Test Conditions
T
A
= 25°C, f
0
= 1 MHz, V
CC
= 5.0V
Max.
10
Unit
pF
AC Test Loads and Waveforms
5V
OUTPUT
R1=910
Ω
R2=510
Ω
C
L
< 30 pF
(Includes fixture and
probe capacitance)
C
L
R2
[8]
[8]
B923–8
R1
C
L
R
L
V
CC
−
2
R
L
=50
Ω
C
L
< 5 pF
(Includes fixture and
probe capacitance)
(a) TTL AC Test Load
3.0V
3.0V
2.0V
GND
< 1 ns
1.0V
2.0V
(b) PECL AC Test Load
V
IHE
80%
V
ILE
20%
V
IHE
80%
20%
V
ILE
< 1 ns
B923–10
1.0V
< 1 ns
B923–9
< 1 ns
(c) TTL Input Test Waveform
(d) PECL Input Test Waveform
Transmitter Switching Characteristics
Over the Operating Range
[1]
7B923-155
Parameter
t
CKW
t
B
t
CPWH
t
CPWL
t
SD
t
HD
t
SENP
t
HENP
t
PDR
t
PPWH
t
PDF
t
RISE
t
FALL
t
DJ
t
RJ
t
RJ
Write Clock Cycle
Bit Time
[9]
CKW Pulse Width HIGH
CKW Pulse Width LOW
Data Set-Up Time
[10]
Data Hold Time
[10]
Enable Set-Up Time (to insure correct RP)
[11]
Enable Hold Time (to insure correct RP)
[11]
Read Pulse Rise Alignment
[12]
Read Pulse HIGH
[12]
Read Pulse Fall Alignment
[12]
7B923
Min.
30.3
3.03
6.5
6.5
5
0
6t
B
+ 8
0
Max
62.5
6.25
7B923-400
Min.
25
2.5
6.5
6.5
5
0
6t
B
+ 8
0
2
−4
4t
B
−3
6t
B
−3
2
Max
62.5
6.25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.2
1.2
35
175
20
ns
ns
ps
ps
ps
Description
Min.
62.5
6.25
6.5
6.5
5
0
6t
B
+ 8
0
−4
4t
B
−3
6t
B
−3
Max
66.7
6.67
2
−4
4t
B
−3
6t
B
−3
PECL Output Rise Time 20−80% (PECL Test Load)
[7]
PECL Output Fall Time 80−20% (PECL Test Load)
[7]
Deterministic Jitter (peak-peak)
[7, 13]
Random Jitter (peak-peak)
[7, 14]
Random Jitter (σ)
[7,14]
1.2
1.2
35
175
20
1.2
1.2
35
175
20
Notes:
7. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
8. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
9. Transmitter t
B
is calculated as t
CKW
/10. The byte rate is one tenth of the bit rate.
10. Data includes D
0−7
, SC/D, SVS, ENA, ENN, and BISTEN. t
SD
and t
HD
minimum timing assures correct data load on rising edge of CKW, but not RP function or timing.
11. t
SENP
and t
HENP
timing insures correct RP function and correct data load on the rising edge of CKW.
12. Loading on RP is the standard TTL test load shown in part (a) of AC Test Loads and Waveforms except C
L
= 15 pF.
13. While sending continuous K28.5s, RP unloaded, outputs loaded to 50Ω to V
CC
−2.0V,
over the operating range.
14. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to CKW input, over the operating
range.
9
CYPRESS [ CYPRESS SEMICONDUCTOR ]
