CY7B923
CY7B933
Receiver Switching Characteristics
Over the Operating Range
[1]
7B933-155
Parameter
t
CKR
t
B
t
CPRH
t
CPRL
t
RH
t
PRF
t
PRH
t
A
t
ROH
t
H
t
CKX
t
CPXH
t
CPXL
t
DS
t
SA
t
EFW
Description
Read Clock Period (No Serial Data Input), REFCLK
as Reference
[15]
Bit Time
[16]
Read Clock Pulse HIGH
Read Clock Pulse LOW
RDY Hold Time
RDY Pulse Fall to CKR Rise
RDY Pulse Width HIGH
Data Access Time
[17, 18]
Data Hold Time
[17, 18]
Data Hold Time from CKR Rise
[17, 18]
REFCLK Clock Period Referenced to CKW of
Transmitter
[19]
REFCLK Clock Pulse HIGH
REFCLK Clock Pulse LOW
Propagation Delay SI to SO (note PECL and TTL
thresholds)
[20]
Static Alignment
[7, 21]
Error Free Window
[7, 22]
0.9t
B
Min.
−1
6.25
5t
B
−3
5t
B
−3
t
B
−2.5
5t
B
−3
4t
B
−3
2t
B
−2
t
B
−2.5
2t
B
−3
−0.1
6.5
6.5
20
100
0.9t
B
+0.1
2t
B
+
4
Max
+1
6.67
7B933
Min.
−1
3.03
5t
B
−3
5t
B
−3
t
B
−2.5
5t
B
−3
4t
B
−3
2t
B
−2
t
B
−2.5
2t
B
−3
−0.1
6.5
6.5
20
100
0.9t
B
+0.1
2t
B
+4
Max.
+1
6.25
7B933-400
Min.
−1
2.5
5t
B
−3
5t
B
−3
t
B
−2.5
5t
B
−3
4t
B
−3
2t
B
−2
t
B
−2.5
2t
B
−3
−0.1
6.5
6.5
20
100
+0.1
2t
B
+4
Max.
+1
6.25
Unit
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
ps
Notes:
15. The period of t
CKR
will match the period of the transmitter CKW when the receiver is receiving serial data. When data is interrupted, CKR may drift to one of the range limits
above.
16. Receiver t
B
is calculated as t
CKR
/10 if no data is being received, or t
CKW
/10 if data is being received. See note.
17. Data includes Q
0−7
, SC/D, and RVS.
18. t
A
, t
ROH
, and t
H
specifications are only valid if all outputs (CKR, RDY, Q
0−7
, SC/D, and RVS) are loaded with similar DC and AC loads.
19. REFCLK has no phase or frequency relationship with CKR and only acts as a centering reference to reduce clock synchronization time. REFCLK must be
within 0.1% of the transmitter CKW frequency, necessitating a
±500-PPM
crystal.
20. The PECL switching threshold is the midpoint between the PECL− V
OH
, and V
OL
specification (approximately V
CC
−
1.35V). The TTL switching threshold is 1.5V.
21. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in
3,000 nominal transitions until a byte error occurs.
22. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
over the operating range, input jitter
<
50% Dj.
10
CYPRESS [ CYPRESS SEMICONDUCTOR ]
