CY7B923
CY7B933
CY7B923
DON'T CARE
DON'T CARE
FOTO
MODE
BIST
LOOP
WITHIN SPEC.
CKW
RP
DON'T CARE
DON'T CARE
SC/D
OUTA
OUTB
OUTC
D
0 − 7
8
LOW
SVS
ENA
ENN
HIGH
Tx
START
Tx
STOP
BISTEN
CY7B933
WITHIN SPEC.
DON'T CARE
LOW
REFCLK
MODE
RF
SO
CKR
DON'T CARE
SC/D
INA
Q
0 − 7
8
ERROR
INB
A/B
RVS
LOW
BIST
LOOP
TEST
START
RDY
BISTEN
TEST
END
Rx
BEGIN
TEST
B923–23
Figure 7. Built In Self-Test Illustration
BIST Mode
3. Allow the Transmitter to run through several BIST loops or
until the Receiver test is complete. RP will pulse LOW once
per BIST loop, and can be used by an external counter to
monitor the number of test pattern loops.
BIST mode functions as follows:
1. Set BISTEN LOW to begin test pattern generation. Trans-
mitter begins sending bit rate ...1010...
4. When testing is completed, set BISTENHIGH and ENA and
ENN HIGH and resume normal function.
2. Set either ENA or ENN LOW to begin pattern sequence
generation (use of the Enable pin not being used for normal
FIFO or system interface can minimize logic delays be-
tween the controller and transmitter).
Note: It may be advisable to send violation characters to test
the RVS output in the Receiver. This can be done by explicitly
sending a violation with the SVS input, or allowing the trans-
17
CYPRESS [ CYPRESS ]
