CY7B923
CY7B933
ASYNCHRONOUS FIFO
7C42X/3X/6X/7X
CLOCKED FIFO
7C44X/5X
R
Q
ENR
ENN
CKR
Q
0 − 8
0 − 8
9
9
ENA
CKW
RP
D
,SC/D
CKW
D
,SC/D
0 − 7
0 − 7
7B923
7B923
HOTLINK TRANSMITTER
HOTLINK TRANSMITTER
HOTLINK RECEIVER
7B933
HOTLINK RECEIVER
7B933
CKR
RDY
Q
,SC/D
9
CKR
RDY
Q
,SC/D
9
0 − 7
0 − 7
W
7C42X/3X/6X/7X
D
0 − 8
CKW
ENW
D
0 − 8
7C44X/5X
B923–21
ASYNCHRONOUS FIFO
CLOCKED FIFO
Figure 5. Seamless FIFO Interface
Bypass Mode Operation
to maintain proper link synchronization (in Bypass mode the proper
senseof running disparity cannot be guaranteedfor the first pad char-
acter, but is correct for all pad characters that follow). This automatic
insertion of pad characters can be inhibited byinsuring that the Trans-
mitter is always enabled (i.e., ENA or ENN is hard-wired LOW).
In Bypass mode the input data is interpreted as ten (10) bits
(D ), SC/D (Da), and SVS (Dj) of pre-encoded transmission data to
b-h
be serialized and sent over the link. This data can use any encoding
method suitable to the designer. The only restrictions upon the data
encoding method is that it contain suitable transition density for the
Receiver PLL data synchronizer (one per 10 bit byte), and that it be
compatible with the transmission media.
PECL Output Functional and Connection Options
The three pairs of PECL outputs all contain the same informa-
tion and are intended for use in systems with multiple connec-
tions. Each output pair may be connected to a different serial
media, each of which may be a different length, link type, or
interface technology. For systems that do not require all three
Data loaded into the Input register on the rising edge of CKW
will be loaded into the Shifter on the subsequent rising edges
of CKW. It will then be shifted to the outputs one bit at a time
using the internal clock generated by the clock generator. The
first bit of the transmission character (Da)will appear at theoutput
(OUTA±, OUTB±, and OUTC±) after the next CKW edge.
output pairs, the unused pairs should be wired to V
to mini-
CC
mize the power dissipated by the output circuit, and to minimize un-
wanted noise generation. An internal voltage comparator detects
While in either the Encoded mode or Bypass mode, if a CKW
edge arrives when the inputs are not enabled (ENA and ENN
both HIGH), the Encoder will insert a pad character K28.5 (e.g., C5.0)
when an output differential pair is wired to V , causing the current
source for that pair to be disabled. This results in a power savings of
around 5 mA for each unused pair.
CC
15
CYPRESS [ CYPRESS ]
