CY62148E MoBL
®
Figure 3. Data Retention Waveform
DATA RETENTION MODE
V
CC
V
CC(min)
t
CDR
V
DR
> 2.0 V
V
CC(min)
t
R
CE
Switching Characteristics
Over the operating range
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
Data setup to write end
Data hold from write end
WE LOW to high Z
WE HIGH to low Z
45
35
35
0
0
35
25
0
–
10
–
–
–
–
–
–
–
–
18
–
55
40
40
0
0
40
25
0
–
10
–
–
–
–
–
–
–
–
20
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
CE LOW to power-up
CE HIGH to power-down
45
–
10
–
–
5
–
10
–
0
–
45
–
45
–
45
22
–
18
–
18
55
–
10
–
–
5
–
10
–
0
–
–
55
–
55
25
–
20
–
20
–
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45 ns
Description
Min
Max
Min
55 ns
Unit
Max
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels
of 0 to 3 V, and output loading of the specified I
OL
/I
OH
as shown in the
15. SOIC package is available only in 55 ns speed bin.
16. At any temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any device.
17. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
18. The internal wre.ite time of the memory is defined by the overlap of WE, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05442 Rev. *H
Page 6 of 14
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