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CY62148ELL-45ZSXI 参数 Datasheet PDF下载

CY62148ELL-45ZSXI图片预览
型号: CY62148ELL-45ZSXI
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 512K的× 8 )静态RAM [4-Mbit (512 K × 8) Static RAM]
分类和应用: 内存集成电路静态存储器光电二极管
文件页数/大小: 14 页 / 407 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY62148E MoBL
®
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature with
power applied .......................................... –55 °C to + 125 °C
Supply voltage to
ground potential.................. –0.5 V to 6.0 V (V
CCmax
+ 0.5 V)
DC voltage applied to outputs
in high Z state
.............. –0.5 V to 6.0 V (V
CCmax
+ 0.5 V)
DC input voltage
.......... –0.5 V to 6.0 V (V
CCmax
+ 0.5 V)
Output current into outputs (LOW) .............................. 20 mA
Static discharge voltage........................................... > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up current ......................................................>200 mA
Operating Range
Device
CY62148E
Range
Ambient
Temperature
V
CC
Industrial/
–40 °C to +85 °C 4.5 V to 5.5 V
Automotive-A
Electrical Characteristics
Over the operating range
Parameter
V
OH
V
OL
V
IH
V
IL
Description
Test Conditions
45 ns
Min
2.4
2.2
–0.5
–1
–1
Typ
15
2
1
Max
0.4
V
CC
+ 0.5
0.8
+1
+1
20
2.5
7
Min
2.4
2.2
–0.5
–1
–1
55 ns
Typ
15
2
1
Max
0.4
V
CC
+ 0.5
0.6
+1
+1
20
2.5
7
µA
µA
µA
mA
Unit
V
V
V
V
Output HIGH voltage I
OH
= –1 mA
Output LOW voltage I
OL
= 2.1 mA
Input HIGH voltage
Input LOW voltage
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V For TSOPII
package
For SOIC
package
I
IX
I
OZ
I
CC
I
SB2 [9]
Input leakage current GND < V
I
< V
CC
Output leakage
current
GND < V
O
< V
CC
, output disabled
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
V
CC
operating supply f = f
max
= 1/t
RC
current
f = 1 MHz
Automatic CE
power-down current
— CMOS inputs
CE > V
CC
– 0.2 V
V
IN
> V
CC
– 0.2 V or V
IN
< 0.2 V,
f = 0, V
CC
= V
CC(max)
Notes
3. V
IL(min)
= –2.0 V for pulse durations less than 20 ns for I < 30 mA.
4. V
IH(max)
= V
CC
+ 0.75 V for pulse durations less than 20 ns.
5. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V
CC
(min) and 200 µs wait time after V
CC
stabilization.
6. SOIC package is available only in 55 ns speed bin.
7. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25 °C.
8. Under DC conditions the device meets a V
IL
of 0.8 V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6 V.
This is applicable to SOIC package only. Refer to
for details.
9. Chip enable (CE) must be HIGH at CMOS level to meet the I
SB2
/ I
CCDR
spec. Other inputs can be left floating.
Document #: 38-05442 Rev. *H
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