Ultra37000 CPLD Family
Logic Block Diagrams (continued)
Clock/
Input
Input
1
CY37256/CY37256V (256-lead BGA)
4
4
4
36
36
LOGIC
BLOCK
A
LOGIC
BLOCK
P
12 I/Os
I/O0−I/O11
12 I/Os
16
36
16
36
16
36
16
36
16
16
36
I/O180−I/O191
12 I/Os
12 I/Os
LOGIC
BLOCK
B
LOGIC
BLOCK
O
16
36
16
36
16
I/O168−I/O179
I/O12−I/O23
12 I/Os
12 I/Os
LOGIC
BLOCK
C
LOGIC
BLOCK
N
I/O156−I/O167
I/O24−I/O35
12 I/Os
12 I/Os
LOGIC
BLOCK
D
LOGIC
BLOCK
M
I/O36−I/O47
I/O144−I/O155
PIM
36
16
36
16
12 I/Os
12 I/Os
LOGIC
BLOCK
E
LOGIC
BLOCK
L
I/O48−I/O59
I/O132−I/O143
36
16
12 I/Os
12 I/Os
LOGIC
BLOCK
F
LOGIC
BLOCK
K
I/O120−I/O131
I/O60−I/O71
36
16
36
16
36
12 I/Os
12 I/Os
LOGIC
BLOCK
G
LOGIC
BLOCK
J
I/O72−I/O83
I/O108−I/O119
36
16
12 I/Os
12 I/Os
I/O84−I/O95
LOGIC
BLOCK
H
LOGIC
BLOCK
I
16
I/O96−I/O107
TDI
TCK
TMS
96
96
JTAG Tap
Controller
TDO
Document #: 38-03007 Rev. *C
Page 11 of 62
CYPRESS [ CYPRESS ]
