Ultra37000 CPLD Family
0
1
TO CLOCK MUX ON
ALL INPUT MACROCELLS
O
INPUT/CLOCK PIN
C12
0
O
1
TO CLOCK MUX
IN EACH
LOGIC BLOCK
C13, C14, C15
OR C16
0
1
2
3
O
TO PIM
CLOCK POLARITY MUX
ONE PER LOGIC BLOCK
FOR EACH CLOCK INPUT
D
D
0
Q
Q
Q
FROM CLOCK
POLARITY INPUT
CLOCK PINS
1
O
2
3
C10C11
C8
C9
D
LE
Figure 4. Input/Clock Macrocell
Clocking
The Ultra37000 features:
• No fanout delays
• No expander delays
• No dedicated vs. I/O pin delays
• No additional delay through PIM
Each I/O and buried macrocell has access to four synchronous
clocks (CLK0, CLK1, CLK2 and CLK3) as well as an
asynchronous product term clock PTCLK. Each input
macrocell has access to all four synchronous clocks.
• No penalty for using 0–16 product terms
• No added delay for steering product terms
• No added delay for sharing product terms
• No routing delays
Dedicated Inputs/Clocks
Five pins on each member of the Ultra37000 family are desig-
nated as input-only. There are two types of dedicated inputs
on Ultra37000 devices: input pins and input/clock pins.
Figure 3 illustrates the architecture for input pins. Four input
options are available for the user: combinatorial, registered,
double-registered, or latched. If a registered or latched option
is selected, any one of the input clocks can be selected for
control.
• No output bypass delays
The simple timing model of the Ultra37000 family eliminates
unexpected performance penalties.
COMBINATORIAL SIGNAL
Figure 4 illustrates the architecture for the input/clock pins.
Like the input pins, input/clock pins can be combinatorial,
registered, double-registered, or latched. In addition, these
pins feed the clocking structures throughout the device. The
clock path at the input has user-configurable polarity.
t
= 6.5 ns
PD
INPUT
OUTPUT
OUTPUT
REGISTERED SIGNAL
= 3.5 ns
t
t
= 4.5 ns
S
CO
Product Term Clocking
D,T,L
O
INPUT
In addition to the four synchronous clocks, the Ultra37000
family also has a product term clock for asynchronous
clocking. Each logic block has an independent product term
clock which is available to all 16 macrocells. Each product term
clock also supports user configurable polarity selection.
CLOCK
Figure 5. Timing Model for CY37128
Timing Model
One of the most important features of the Ultra37000 family is
the simplicity of its timing. All delays are worst case and
system performance is unaffected by the features used. Figure
5 illustrates the true timing model for the 167-MHz devices in
high speed mode. For combinatorial paths, any input to any
output incurs a 6.5-ns worst-case delay regardless of the
amount of logic used. For synchronous systems, the input set-
up time to the output macrocells for any input is 3.5 ns and the
clock to output time is also 4.0 ns. These measurements are
for any output and synchronous clock, regardless of the logic
used.
JTAG and PCI Standards
PCI Compliance
5V operation of the Ultra37000 is fully compliant with the PCI
Local Bus Specification published by the PCI Special Interest
Group. The 3.3V products meet all PCI requirements except
for the output 3.3V clamp, which is in direct conflict with 5V
tolerance. The Ultra37000 family’s simple and predictable
timing model ensures compliance with the PCI AC specifica-
tions independent of the design.
Document #: 38-03007 Rev. *C
Page 7 of 62
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