Ultra37000 CPLD Family
Logic Block Diagrams (continued)
Clock/
Input
CY37384/CY37384V (256-Lead BGA)
Input
1
4
4
4
36
16
36
16
36
16
36
16
36
LOGIC
BLOCK
AA
LOGIC
BLOCK
BL
12 I/Os
I/O0−I/O11
16
36
12 I/Os
12 I/Os
I/O12−I/O23
LOGIC
BLOCK
AB
LOGIC
BLOCK
BK
16
36
16
36
16
36
I/O168−I/O191
12 I/Os
12 I/Os
I/O24−I/O35
LOGIC
BLOCK
AC
LOGIC
BLOCK
BJ
I/O156−I/O179
12 I/Os
LOGIC
BLOCK
AD
LOGIC
BLOCK
BI
I/O144−I/O167
36
16
PIM
12 I/Os
I/O36−I/O47
LOGIC
BLOCK
AE
LOGIC
BLOCK
BH
16
36
16
36
16
12 I/Os
LOGIC
BLOCK
AF
LOGIC
BLOCK
BG
I/O132−I/O155
36
16
36
16
36
16
36
16
12 I/Os
I/O48−I/O59
LOGIC
BLOCK
AG
LOGIC
BLOCK
BF
36
16
12 I/Os
12 I/Os
I/O60−I/O71
LOGIC
BLOCK
AH
LOGIC
BLOCK
BE
I/O120−I/O143
36
16
12 I/Os
12 I/Os
I/O72−I/O83
LOGIC
BLOCK
AI
LOGIC
BLOCK
BD
I/O108−I/O131
36
16
36
16
12 I/Os
LOGIC
BLOCK
AJ
LOGIC
BLOCK
BC
I/O96−I/O119
36
16
36
16
12 I/Os
I/O84−I/O95
LOGIC
BLOCK
AK
LOGIC
BLOCK
BB
36
16
36
16
12 I/Os
LOGIC
BLOCK
AL
LOGIC
BLOCK
BA
I/O96−I/O107
TDI
TCK
TMS
JTAG Tap
Controller
96
96
TDO
Document #: 38-03007 Rev. *C
Page 12 of 62
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