CY28800
Byte 2: Control Register 2
(continued)
Bit
4
@pup
0
Name
SRC_STP_DIF[T/C]4
Description
Allow Control DIF[T/C]4 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]3 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]2 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]1 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]0 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
3
0
SRC_STP_DIF[T/C]3
2
0
SRC_STP_DIF[T/C]2
1
0
SRC_STP_DIF[T/C]1
0
0
SRC_STP_DIF[T/C]0
Byte 3: Control Register 3
Bit
7
6
5
4
3
2
1
0
@pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Byte 4: Vendor ID Register
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
1
0
0
0
Name
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
Byte 5: Control Register 5
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
0
0
0
0
0
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Document #: 38-07723 Rev *B
Page 5 of 16
CYPRESS [ CYPRESS SEMICONDUCTOR ]
