CY28800
Byte 0: Control Register 0
Bit
7
6
5
4
3
2
1
0
@pup
0
0
0
0
0
1
1
1
Name
PWRDWN Drive Mode
SRC_STP Drive Mode
Reserved
Reserved
Reserved
HIGH_BW#
PLL/BYPASS#
SRC_DIV2#
Description
Power Down drive mode
0 = Driven when stopped, 1 = Tri-state
SRC Stop drive mode
0 = Driven when stopped, 1 = Tri-state
Reserved
Reserved
Reserved
HIGH_BW#
0 = High Bandwidth, 1 = Low bandwidth
PLL/BYPASS#
0 = Fanout buffer, 1 = PLL mode
SRC_DIV2# configures output frequency at half the input frequency
0 = Divided by 2 mode (output = input/2),1 = Normal (output = input)
Byte 1: Control Register 1
Bit
7
@pup
1
OE_7
Name
DIF[T/C]7 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]6 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]5 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]4 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]3 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]2 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]1 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
DIF[T/C]0 Output Enable
0 = Disabled (Tri-state)
1 = Enabled
Description
6
1
OE_6
5
1
OE_5
4
1
OE_4
3
1
OE_3
2
1
OE_2
1
1
OE_1
0
1
OE_0
Byte 2: Control Register 2
Bit
7
@pup
0
Name
SRC_STP_DIF[T/C]7
Description
Allow Control DIF[T/C]7 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]6 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
Allow Control DIF[T/C]5 with assertion of SRC_STP
0 = Free-running
1 = Stopped with SRC_STP
6
0
SRC_STP_DIF[T/C]6
5
0
SRC_STP_DIF[T/C]5
Document #: 38-07723 Rev *B
Page 4 of 16
CYPRESS [ CYPRESS SEMICONDUCTOR ]
