CY28800
100-MHz Differential Buffer for PCI Express
and SATA
Features
• CK409 and CK410 companion buffer
• Eight differential 0.7V clock output pairs
• OE_INV input for inverting OE, PWRDWN, and
SRC_STP active levels
• Individual OE controls
• Low CTC jitter (< 50 ps)
• Programmable bandwidth
• SRC_STP power management control
• SMBus Block/Byte/Word Read and Write support
• 3.3V operation
• PLL Bypass-configurable
• Divide by 2 programmable
• 48-pin SSOP package
Functional Description
The CY28800 is a differential buffer and serves as a
companion device to the CK409 or CK410 clock generator.
The device is capable of distributing the Serial Reference
Clock (SRC) in PCI Express and SATA implementations.
Block Diagram
SRC_DIV2#
VDD
VSS
SRCT_IN
SRCC_IN
OE_0
OE_3
DIFT0
DIFCO
VSS
VDD
DIFT1
DIFC1
OE_1
OE_2
DIFT2
DIFC2
VSS
VDD
DIFT3
DIFC3
PLL/BYPASS#
SCLK
SDATA
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD_A
VSS_A
IREF
LOCK
OE_7
OE_4
DIFT7
DIFC7
OE_INV
VDD
DIFT6
DIFC6
OE_6
OE_5
DIFT5
DIFC5
VSS
VDD
DIFT4
DIFC4
HIGH_BW#
SRC_STP
PWRDWN
VSS
PWRDWN
OE_[7:0]
OE_INV
SRC_STP
SCLK
SDATA
SMBus Controller
Output Control
DIFT_0
DIFC_0
DIFT_1
DIFC_1
DIFT_2
DIFC_2
DIFT_3
DIFC_3
PLL/BYPASS#
DIV
SRCT_IN
SRCC_IN
DIFT_4
DIFC_4
DIFT_5
DIFC_5
DIFT_6
DIFC_6
DIFT_7
DIFC_7
HIGH_BW#
PLL1
CY28800
SRC_DIV2#
Output
Buffer
48 SSOP
Cypress Semiconductor Corporation
Document #: 38-07723 Rev *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 30, 2006
CYPRESS [ CYPRESS SEMICONDUCTOR ]
