CY28800
Pin Description
Pin
4,5
Name
SRCT_IN, SRCC_IN
Type
I,DIF
0.7V Differential inputs
Description
8,9;12,13;16,17;20,21; 30,29; DIF[T/C][7:0]
34,33;38,37;42,41
6,7,14,15,35,36,43,44
OE_[7:0]
O,DIF
0.7V Differential Clock Outputs
I,SE
3.3V LVTTL input for enabling differential outputs
Active High if OE_INV = 0
Active Low if OE_INV = 1
3.3V LVTTL input for selecting PLL bandwidth
0 = High BW, 1 = Low BW
3.3V LVTTL output, transitions high when PL lock is
achieved (latched output)
3.3V LVTTL input for Power Down
Active Low if OE_INV = 0
Active High if OE_INV = 1
3.3V LVTTL input for selecting input frequency divided by
two, active low
3.3V LVTTL input for SRC_STP.
Disables stoppable outputs.
Active Low if OE_INV = 0
Active High if OE_INV = 1
SMBus Slave Clock Input
A precision resistor is attached to this pin to set the differ-
ential output current
3.3V LVTTL input for selecting fan-out or PLL operation
3.3V Power Supply for PLL
Ground for PLL
Ground for outputs
3.3V power supply for outputs
Input strap for setting polarity of OE_[7:0], SRC_STP, and
PWRDWN
28
45
26
HIGH_BW#
LOCK
PWRDWN
I,SE
O,SE
I,SE
1
27
SRC_DIV2#
SRC_STP
I,SE
I,SE
23
24
46
22
48
47
3,10,18,25,32
2,11,19,31,39
40
SCLK
SDATA
IREF
PLL/BYPASS#
VDD_A
VSS_A
VSS
VDD
OE_INV
I,SE
I
I
PWR
GND
GND
PWR
I, SE
I/O,OC
Open collector SMBus data
Serial Data Interface
To enhance the flexibility and function of the clock buffer, a
two-signal serial interface is provided. Through the Serial Data
Interface, various device functions, such as individual clock
output buffers, can be individually enabled or disabled. The
registers associated with the Serial Data Interface initializes to
their default setting upon power-up, and therefore use of this
interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for
power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in
Table 1.
The block write and block read protocol is outlined in
Table 2
while
Table 3
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11011100 (DCh).
Table 1. Command Code Definition
Bit
7
(6:0)
0 = Block read or block write operation
1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Description
Document #: 38-07723 Rev *B
Page 2 of 16
CYPRESS [ CYPRESS SEMICONDUCTOR ]
