CY2273A
Switching Characteristics for CY2273A-3
[8]
Over the Operating Range
Parameter
t
1
t
2
Output
All
CPUCLK,
IOAPIC
REF0
USBCLK
SDRAM
PCI
CPUCLK
CPUCLK
CPUCLK
CPUCLK,
PCICLK
CPUCLK,
SDRAM
PCICLK,
PCICLK
CPUCLK,
SDRAM
PCICLK
CPUCLK,
PCICLK,
SDRAM
Description
Output Duty Cycle
[9]
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
Test Conditions
t
1
= t
1A
÷
t
1B
Between 0.4V and 2.0V, V
DDCPU
= 2.5V
Between 0.4V and 2.4V, V
DDCPU
= 3.3V
Min.
45
0.75
Typ.
50
1.0
Max.
55
4.0
Unit
%
V/ns
t
2
t
2
REF0 and USBCLK Ris- Between 0.4V and 2.4V
ing and Falling Edge Rate
SDRAM and PCI Clock
Rising and Falling Edge
Rate
CPU Clock Rise Time
CPU Clock Fall Time
CPU-CPU Clock Skew
CPU-PCI Clock Skew
CPU-SDRAM Clock
Skew
PCI-PCI Clock Skew
Cycle-Cycle Clock Jitter
Cycle-Cycle Clock Jitter
Power-up Time
Between 0.4V and 2.4V
1.0
0.85
1.0
4.0
4.0
V/ns
V/ns
t
3
t
4
t
5
t
6
t
7
t
8
t
10
t
10
t
11
Between 0.4V and 2.0V, V
DDCPU
= 2.5V
Between 0.4V and 2.4V, V
DDCPU
= 3.3V
Between 2.0V and 0.4V, V
DDCPU
= 2.5V
Between 2.4V and 0.4V, V
DDCPU
= 3.3V
Measured at 1.25V, V
DDCPU
= 2.5V
Measured at 1.5V, V
DDCPU
= 3.3V
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
Measured at 1.5V
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
Measured at 1.5V
CPU, PCI, AGP, and SDRAM clock sta-
bilization from power-up
0.4
0.5
0.4
0.5
100
2.13
2.67
2.13
2.67
300
900
600
500
750
500
3
ns
ns
ps
ps
ps
ps
ps
ps
ms
8
CYPRESS [ CYPRESS SEMICONDUCTOR ]
