CY2273A
Actual Clock Frequency Values
Clock Output
CPUCLK
CPUCLK
CPUCLK
CPUCLK
USBCLK
Target
Frequency
(MHz)
66.67
60.0
75.0
83.33
48.0
Actual
Frequency
(MHz)
66.654
60.0
75.0
83.138
48.008
0
0
–1947
167
PPM
–195
• Output impedance: 25Ω (typical) measured at 1.5V
Power Management Logic
[3]
- Active when MODE pin is held ‘LOW’
CPU_STOP
X
0
0
1
1
PCI_STOP PWR_DWN
X
0
1
0
1
0
1
1
1
1
CPUCLK
Low
Low
Low
Low
Low
33/30 MHz
PCICLK
PCICLK_F
Stopped
Running
Running
Running
Running
Other
Clocks
Stopped
Running
Running
Running
Running
Osc.
Off
PLLs
Off
Running Running
Running Running
Running Running
Running Running
60/66/75/83 MHz Low
60/66/75/83 MHz 30/33/30/33 MHz
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• I
2
C Address for the CY2273 is:
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit
Pin #
Description
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’
Bit 1
1
1
0
0
Bit 0
1 - Three-State
0 - N/A
1 - Testmode
0 - Normal Operation
Bit 7 --
Bit 6 --
Bit 5 --
Bit 4 --
Bit 3 --
Bit 2 --
Bit 1 --
Bit 0
Select Functions
Outputs
Functional Description
Three-State
Test Mode
[5]
-2 only
Ref
Hi-Z
TCLK
IOAPIC
Hi-Z
TCLK
USBCLK
Hi-Z
TCLK/2
AGP
Hi-Z
TCLK/2
CPU
Hi-Z
TCLK/2
[4]
PCI, PCI_F
Hi-Z
TCLK/4
SDRAM
Hi-Z
TCLK/2
Notes:
3. AGP clocks are driven on PCICLK5 and PCICLK4 on -2 option. These clocks behave similar to the PCICLK_F output, in that they are free-running and stop
only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table.
4. TCLK supplied on the XTALIN pin in Test Mode.
5. Valid only for SEL1=0.
4
CYPRESS [ CYPRESS SEMICONDUCTOR ]
