CY2273APVC-1 参数 Datasheet PDF下载

CY2273A

Switching Waveforms

(continued)

CPU_STOP

[11, 12]

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK

(Free-Running)

CPU_STOP

CPUCLK

(External)

PCI_STOP

[13, 14]

CPUCLK

(Internal)

PCICLK

(Internal)

PCICLK

(Free-Running)

PCI_STOP

PCICLK

(External)

PWR_DOWN

CPUCLK

(Internal)

PCICLK

(Internal)

PWR_DWN

CPUCLK

(External)

PCICLK

(External)

VCO

Crystal

Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.

Timing Requirements for the I

2

C Bus

SDA

t

13

SCL

t

14

t

15

t

20

t

21

t

14

t

18

t

16

t

19

t

17

t

22

Notes:

11. CPUCLK on and CPUCLK off latency is 2 or 3 CPUCLK cycles.

12. CPU_STOP may be applied asynchronously. It is synchronized internally.

13. PCICLK on and PCICLK off latency is 1 rising edge of the external PCICLK.

14. PCI_STOP may be applied asynchronously. It is synchronized internally.

11