CY2273A
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
Application Circuit
Summary
• A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C
LOAD
of
this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different
C
LOAD
is used. Footprints must be laid out for flexibility.
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1
µF.
In some cases, smaller value capacitors may be required.
• The value of the series terminating resistor satisfies the following equation, where R
trace
is the loaded characteristic impedance
of the trace, R
out
is the output impedance of the clock generator (specified in the data sheet), and R
series
is the series terminating
resistor.
R
series
> R
trace
– R
out
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
• A Ferrite Bead
may
be used to isolate the Board V
DD
from the clock generator V
DD
island. Ensure that the Ferrite Bead offers
greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout
and Termination Techniques for Cypress Clock Generators” for more details.
• If a Ferrite Bead is used, a 10
µF–
22
µF
tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor
prevents power supply droop during current surges.
12
CYPRESS [ CYPRESS SEMICONDUCTOR ]
