PRELIMINARY
CYW54907
1. Overview
1.1 Introduction
The Cypress CYW54907 is a single-chip device that provides the highest level of integration for an embedded system-on-a-chip with
integrated IEEE 802.11 a/b/g/n/ac MAC/baseband/radio and a separate ARM Cortex-R4 applications processor. It provides a small
form-factor solution with minimal external components to drive down cost for mass volumes and allows for an embedded system with
flexibility in size, form, and function. Comprehensive power management circuitry and software ensure that the system can meet the
needs of highly embedded systems that require minimal power consumption and reliable operation.
Figure 1 shows the interconnect of all the major physical blocks in the CYW54907 and their associated external interfaces, which are
described in greater detail in Section 5. “Applications Subsystem External Interfaces”.
Figure 1. Block Diagram and I/O
CYW54907
SPI Flash
GPIO[16:0]
2x 2-Wire UART
4-Wire UART
2x I2S
RF TX
RF RX
APPS Subsystem
WLAN Subsystem
ARM Cortex‐R4
320 MHz
32 KB I‐cache
32 KB D‐cache
ARM Cortex‐R4
160 MHz
448 KB ROM TCM
576 KB SRAM TCM
2x SPI/CSC
2x CSC
Switch Control
Antenna Diversity
JTAG/SWD
2 MB SRAM
640 KB ROM
802.11ac
1x1
2.4 GHz and 5 GHz
10/100 Ethernet
SDIO 3.0/gSPI
USB 2.0
VDDIOs
GND
WAKE
1.1.1 Features
The CYW54907 supports the following features:
■ ARM Cortex-R4 clocked at 160 MHz (in 1× mode) or up to 320 MHz (in 2× mode).
■ 2 MB of SRAM and 640 KB ROM available for the applications processor.
■ One high-speed 4-wire UART interface with operation up to 4 Mbps.
■ Two low-speed 2-wire UART interfaces multiplexed on general purpose I/O (GPIO) pins.
■ Two dedicated CSC1 interfaces.
■ Two SPI master/slave interfaces with operation up to 24 MHz.
2
1. Cypress Serial Control (CSC) is an I C-compatible interface.
Document Number: 002-19312 Rev. *C
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