PRELIMINARY
CYW54907
Figure 2. Typical Power Topology (Page 1 of 2)
WLRF TX Mixer and PA (not always)
1.2V
Cap-less
LNLDO
WLRF LOGEN
CYW54907 1.2V
Cap-less
LNLDO
1.2V
1.2V
WLRF LNA
VBAT
Operational:
Performance:
Cap-less
VCOLDO
2.3V to 4.8V
3.0V to 4.8V
WLRF AFE and TIA
WLRF TX
Absolute Maximum: 5.5V
1.2V
1.2V
Cap-less
LNLDO
VDDIO
Operational:
Cap-less
LNLDO
WLRF ADC REF
WLRF XTAL
3.3V
15 mA
1.2V
XTAL LDO
Mini‐PMU
(Inside WL Radio)
WLRF RFPLL, PFD, and MMD
Audio PLL
VBAT
1.35V
1.2V
LNLDO
Core Buck
Regulator
(CBUCK)
1.2V
VDDIO
1.35V
BBPLL
LNLDO
WL BBPLL/DFLL
LPLDO1
REG_ON
1.3V, 1.2V,
.095V (AVS)
WLAN/CLB/Top, Always On
WL PHY
CLDO
WL Subcore
WL VDDM (SRAMS in AOS)
APPS VDDM
Power
switch
Supply bump/pad
Ground bump/pad
External to chip
Supply ball
No power switch
Ground ball
APPS SOCSRAM
APPS Subcore
No dedicated power switch, but internal power‐
down modes and block‐specific power switches
WLAN reset
ball
Document Number: 002-19312 Rev. *C
Page 8 of 95
CYPRESS [ CYPRESS ]
