PRELIMINARY
CYW54907
10. GPIO Signals and Strapping Options
10.1 Overview
This section describes GPIO signals and strapping options. The pins are sampled at power-on reset (POR) to determine various operating modes. Sampling occurs a few
milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in Table 12. Each strapping
option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD
resistor to ground, using a 10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
10.2 Weak Pull-Down and Pull-Up Resistances
At VDDO = 3.3V ±10%, the minimum, typical, and maximum weak pull-down resistances (for a pin voltage of VDDO) are 37.99 kΩ, 44.57 kΩ, and 51.56 kΩ, respectively. At
VDDO = 3.3V ±10%, the minimum, typical, and maximum weak pull-up resistances (for a pin voltage of 0V) are 34.73 kΩ, 39.58 kΩ, and 44.51 kΩ, respectively.
10.3 Strapping Options
Table 11 provides the strapping options.
Table 11. Strapping Options
Default Internal
Pin Name
GPIO_1
Strap
GSPI_MODE
Bump #
142
Description
Pull During Strap
PD
PD
PD
PD
PD
PD
PD
Enable gSPI interface
GPIO_7
WCPU_BOOT_MODE
ACPU_BOOT_MODE
SDIO_MODE
95
Boot from SoC SROM or SoC SRAM
GPIO_11
140
131
145
207
201
Boot from tightly coupled memory (TCM) ROM or TCM RAM
Select either SDIO host mode or SDIO device mode
Enable PMU voltage trimming
GPIO_13
GPIO_15
VTRIM_EN
RF_SW_CTRL_5
RF_SW_CTRL_7
DAP_CLK_SEL
Select XTAL clock or the test clock (tck) for the debug access port (DAP)
PMU resource initialization mode selection
RSRC_INIT_MODE
Document Number: 002-19312 Rev. *C
Page 43 of 95
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