PRELIMINARY
CYW54907
Table 10. Signal Descriptions (Cont.)
Bump Number
Signal Name
Type
Description
Wake up chip from hibernation mode.
Select precise or coarse 32 kHz clock.
279
283
198
HIB_WAKE_B
HIB_LPO_SELMODE
SRSTN
I
I
I
System reset. This active-low signal resets the
backplanes.
I2S Interface
153
154
163
164
161
158
160
162
156
155
I2S_MCLK0
I2S_SCLK0
I/O
M clock
I/O
S clock
I2S_LRCLK0
I2S_SDATAI0
I2S_SDATAO0
I2S_MCLK1
I2S_SCLK1
I2S_LRCLK1
I2S_SDATAI1
I2S_SDATAO1
I/O
LR clock
I
I2S data input
I2S data output
M clock
O
I/O
I/O
S clock
I/O
LR clock
I
I2S data input
I2S data output
O
JTAG Interface
193
JTAG_SEL
I
JTAG select. This pin must be connected to ground if the
JTAG interface is not used.
No Connects
1–5, 7–13, 16–20, 23, 24, 26–34, 36– NO_CONNECT
38, 41, 43–49, 51, 54, 55, 61–70, 179–
181
–
No connect
Power Supplies (Miscellaneous)
OTP_VDD3P3 PWR OTP 3.3V supply
203
138, 216, 217, 252, 254, 267, 268, 271, VDDC
275–277, 280, 281, 285, 286, 289,
309, 314, 316
PWR 1.2V core supply for WLAN
105, 174, 195, 257, 258, 261, 263, 269 VDDIO
PWR I/O supply
199, 208
157, 159
305, 307
255
VDDIO_RF
PWR I/O supply for RF switch control pads (3.3V).
PWR I/O supply for I2S
VDDIO_I2S
VDDIO_RMII
PWR I/O supply for RMII
VDDIO_SD
PWR I/O supply for SDIO
270
HIB_VDDO
PWR I/O supply for hibernation block
PWR 1.2V supply for baseband PLL
PWR 1.2V supply for audio PLL
PWR 3.3V supply for USB 2.0
PWR 3.3V supply for USB 2.0
PWR 3.3V supply for USB 2.0
204
AVDD1P2
192
AVDD1P2_AUDIO
USB2_AVDD33
USB2_AVDD33LDO
USB2_AVDD33IO
166
173
176
Power Supplies (WLAN)
223
WRF_SYNTH_VDD3P3
WRF_PA_VDD3P3
PWR Synthesizer VDD 3.3V supply
PWR 2.4 GHz and 5 GHz PA 3.3V VBAT supply
PWR PMU 1.35V supply
240, 241
227, 228
244
WRF_PMU_VDD1P35
WRF_TXMIX_VDD
PWR 3.3V supply for TX mixer
229
WRF_SYNTH_VDD1P2
WRF_AFE_VDD1P35
PWR 1.2V supply for synthesizer
231
PWR 1.35V supply for the analog front end (AFE)
Document Number: 002-19312 Rev. *C
Page 40 of 95
CYPRESS [ CYPRESS ]
