PRELIMINARY
CYW54907
Table 13. Pin Multiplexing
Function
Pin
1
2
3
4
–
–
–
–
–
–
–
–
5
–
–
–
–
–
–
–
–
6
–
–
–
–
–
–
–
–
7
–
–
–
–
–
–
–
–
8
–
–
–
–
–
–
–
–
9
–
–
–
–
–
–
–
–
10
–
11
–
–
–
–
–
–
–
–
PWM3
PWM4
PWM5
PWM3
PWM4
PWM5
GPIO_5
GPIO_6
GPIO_8
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
–
–
SPI0_MISO SPI0_MISO GPIO_17
SPI0_CLK SPI0_CLK GPIO_18
SPI0_MOSI SPI0_MOSI GPIO_19
–
–
–
SPI0_CS
SPI0_CS
GPIO_20
–
I2C0_SDATA
I2C0_CLK
I2S_MCLK0 I2S_MCLK0
I2S_SCLK0 I2S_SCLK0
I2S_LRCLK0 I2S_LRCLK0
I2C0_SDATA GPIO_21
–
I2C0_CLK
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_29
GPIO_0
GPIO_2
GPIO_3
GPIO_4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I2S_S
I2S_
DATAI0
SDATAI0
I2S_
SDATAO0
I2S_
SDATAO1
I2S_SDATAI I2S_SDATAI1
1
I2S_
SDATAO0
I2S_
SDATAO1
GPIO_27
GPIO_28
GPIO_29
GPIO_5
GPIO_6
GPIO_8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I2S_MCLK1 I2S_MCLK1
I2S_SCLK1 I2S_SCLK1
I2S_LRCLK1 I2S_LRCLK1
GPIO_30
GPIO_31
GPIO_0
GPIO_17
GPIO_30
GPIO_31
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
a. UART_DBG_TX and UART_DBG_RX are for UART1 mentioned in section 5.10 and in the reference schematics. SECI_IN and SECI_OUT are for UART2 mentioned in section 5.10 and
in the reference schematics.
Document Number: 002-19312 Rev. *C
Page 47 of 95
CYPRESS [ CYPRESS ]
