PRELIMINARY
CYW54907
Table 10. Signal Descriptions (Cont.)
Bump Number
Signal Name
Type
Description
SPI Interfaces
Note: Each SPI interface can alternatively be configured and used as a CSC interfacea.
76
78
81
82
83
84
86
80
SPI0_CLK
SPI0_MISO
SPI0_SISO
SPI0_CS
O
SPI clock
I
SPI data master in
SPI data master out
SPI slave select
SPI clock
O
O
SPI1_CLK
SPI1_MISO
SPI1_SISO
SPI1_CS
O
I
SPI data master in
SPI data master out
SPI slave select
O
O
UART Interface
85
91
88
87
UART0_CTS
UART0_RTS
UART0_RXD
UART0_TXD
I
UART clear-to-send
O
UART request-to-send
UART serial input
I
O
UART serial output
USB 2.0
170
167
169
175
184
165
USB2_DM
I/O
I/O
I
USB 2.0 data
USB2_DP
USB 2.0 data
USB2_RREF
USB2_MONCDR
USB2_MONPLL
USB2_DSEL
USB 2.0 reference resistor connection
USB 2.0 CDR monitor
USB 2.0 PLL monitor
O
O
I
USB 2.0 host and device mode selection
Voltage Regulators (Integrated)
108, 113, 122, 125
SR_VDDBAT5V
SR_VLX
I
VBAT.
98, 99, 101, 102, 109, 112
O
I
CBUCK switching regulator output
LNLDO input
115, 116, 120, 127
LDO_VDD1P5
128, 129
221
LDO_VDDBAT5V
WRF_XTAL_VDD1P35
WRF_XTAL_VDD1P2
VOUT_LNLDO
I
LDO VBAT
I
XTAL LDO input (1.35V)
XTAL LDO output (1.2V)
Output of LNLDO
220
O
O
O
O
O
O
O
106
114, 121, 126
118, 119
117
VOUT_CLDO
Output of core LDO
VOUT_3P3
LDO 3.3V output
VOUT_3P3_SENSE
VOUT_CLDO_SENSE
VOUT_BBPLLOUT
Voltage sense pin for LDO 3.3V output
Voltage sense pin for core LDO
Output of baseband PLL
103
107
a. The SPI blocks can be re-purposed as I2C, however the WICED SDK does not support this. Certain I2C features are not available when using
the SPI blocks as I2C. Therefore Cypress does not recommend using the SPI blocks as I2C interfaces.
Document Number: 002-19312 Rev. *C
Page 42 of 95
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