PRELIMINARY
CYW54907
5.7.2 SDIO 3.0—Host Mode
The CYW54907 WLAN section supports SDIO version 3.0, including the new UHS-I modes:
■ DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).
■ HS: High-speed up to 50 MHz (3.3V signaling).
■ SDR12: SDR up to 25 MHz (1.8V signaling).
■ SDR25: SDR up to 50 MHz (1.8V signaling).
■ SDR50: SDR up to 100 MHz (1.8V signaling).
Note: The CYW54907 is backward compatible with SDIO v2.0 devices.
In this mode, the device supports the following features:
■ ADMA2.
■ Out-of-band signaling for card detection, write protection, and I/O voltage levels (which are available on GPIOs).
■ Dynamic, specification-compliant shifting from 3.3V to 1.8V I/Os.
5.8 S/PDIF
S/PDIF is a serial audio data transport format used to connect consumer audio devices such as CD players, DVD players, and
surround-sound receivers. Although S/PDIF can be used to transport uncompressed audio formats, the primary use case for the
CYW54907 S/PDIF interface is to transport multichannel compressed audio for surround-sound applications, especially Dolby Digital
and DTS, to an auxiliary external audio processor.
The CYW54907 can support two S/PDIF interfaces via the I2S_SDATA00 and I2S_SDATA01 pins. Because each S/PDIF interface
uses an I2S data line, only I2S or S/PDIF functionality can be enabled on each I2S interface.
Each S/PDIF interface has the following key requirements:
■ S/PDIF transmissions that conform with IEC 60958-1 (receiver not required).
■ Support for linear PCM audio data that conforms with IEC 60948-3.
■ Support for nonlinear PCM audio data that conforms with IEC 60948-3.
■ Support for priority payload formats that include IEC 61937-3 (AC-3) and IEC 61937-5 (DTS).
■ Support for sample rates from 32 kHz to 192 kHz.
■ Support for 16, 20, and 24-bit audio samples.
■ Support for only one concurrent compressed audio stream.
5.9 SPI Flash
The SPI flash interface supports the following features:
■ A SPI-compatible serial bus.
■ An 80 MHz (maximum) clock frequency.
■ Increased Throughput to 40 MBps in Quad-mode or upto 10 MBps in single Mode2
■ Support for either ×1 or ×4 addresses with ×4 data.
■ 3-bytes and 4-byte addressing modes.
■ A configurable dummy-cycle count that is programmable from 1 to 15.
■ Programmable instructions output to serial flash.
■ An option to change the sampling edge from rising-edge to falling-edge for read-back data when in high-speed mode.
2. Note that the clock needs to be constrained to ~26.67MHz for reliable operation at high operating temperatures. The throughput of the SPI Flash block is therefore
restricted to ~13 MBps for Quad mode and ~3 MBps for single mode.
Document Number: 002-19312 Rev. *C
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