PRELIMINARY
CYW54907
low, and right-channel data is transmitted when I2S_LRCK is high. An embedded 128 × 32-bit single-port SRAM for data processing
enhances the performance of the interface.
An audio PLL generates an internal master clock (for I2S_MCLK0 and I2S_MCLK1) that provides support for various sampling rates.
Note: In I2S slave mode if LRCLK changes on the rising edge of the bit clock, the MSB data bit is set half of a bit cycle after LRCLK.
Table 5 shows the MCLK rates (in MHz) associated with each of the various sample rates. In the table, FS refers to the sample rate
in kHz and typical MCLK rates are shaded.
Table 5. Variable Sample Rate and MCLK Rate Supporta
MCLK Rate (MHz)b
Sample
Rate (kHz)
128 × FS
1.024
192 × FS
1.536
256 × FS
2.048
384 × FS
3.072
512 × FS
4.096
640 × FS
5.12
768 × FS
6.144
8.4672
9.216
12.288
16.9344
18.432
24.576
33.8688
36.864
–
1152 × FS
8
9.216
11.025
12
1.4112
1.536
2.1168
2.304
2.8224
3.072
4.2336
4.608
5.6448
6.144
8.192
11.2896
12.288
16.384
22.5792
24.576
32.768
–
7.056
7.68
10.24
14.112
15.36
20.48
28.224
30.72
–
12.7008
13.824
16
2.048
3.072
4.096
6.144
18.432
22.05
24
2.8224
3.072
4.2336
4.608
5.6448
6.144
8.4672
9.216
25.4016
27.648
32
4.096
6.144
8.192
12.288
16.9344
18.432
24.576
33.8688
36.864
–
36.864
44.1
48
5.6448
6.144
8.4672
9.216
11.2896
12.288
16.384
22.5792
24.576
–
–
–
–
–
–
–
64
8.192
12.288
16.9344
18.432
36.864
88.2
96
11.2896
12.288
24.576
–
–
–
–
–
192
–
–
–
a. All data in the table assumes a crystal frequency of 37.4 MHz.
b. MCLK frequency errors are less than 1 ppb.
For an MCLK specification, see Table 45.
Document Number: 002-19312 Rev. *C
Page 17 of 95
CYPRESS [ CYPRESS ]
