PRELIMINARY
CYW54907
5. Applications Subsystem External Interfaces
5.1 Ethernet MAC Controller (MII/RMII)
The CYW54907 integrates a high performance Ethernet MAC controller. The controller interfaces to an external PHY either over a
Media Independent Interface (MII) or a Reduced Media Independent Interface (RMII). The controller can transmit and receive data at
10 Mbps and 100 Mbps.
5.2 GPIO
There are 17 general-purpose I/O (GPIO) pins available on the CYW54907. The GPIOs can be used to connect to various external
devices.
Upon power-up and reset, these pins are tristated. Subsequently, they can be programmed to be either input or output pins via the
GPIO control register. In addition, the GPIO pins can be assigned to various other functions.
Apart from other functions, GPIOs are used to set bootstrap options and use the JTAG interface for debugging during software
development.
5.3 Cypress Serial Control
The CYW54907 has two Cypress Serial Control (CSC) master interfaces for external communication with codecs, DACs, NVRAM,
etc. The I/O pads can be configured as pull-ups or pull-ups can be installed on the reference design to support a multimaster on an
open drain bus.
The I2C0 CSC master interface can support repeated start, however it does not support clock stretching. The I2C1 CSC master
interface does not support repeated start or clock stretching.. The CSC master can support a maximum clock frequency of 400kHz.
If clock stretching is required a bit banging driver is recommended. Cypress's WICED SDK provides and example of such a bit banging
I2C driver. Note that only I2C0 mentioned in Table 10 is multiplexed with GPIOs and supports bit banging. I2C1 is not multiplexed with
GPIOs and therefore cannot support bit banging.
2
5.4 I S
The CYW54907 has two I2S interfaces for audio signal data. The two interfaces are identical. Each interface supports both Master
and Slave modes.
The following signals apply to the first I2S interface:
■ I2S bit clock: I2S_SCLK0 (sometimes referred to as I2S_BITCLK)
■ I2S word select: I2S_LRCK0 (sometimes referred to as I2S_WS)
■ I2S serial data out: I2S_SDATAO0
■ I2S serial data in: I2S_SDATAI0
■ I2S master clock: I2S_MCLK0
The following signals apply to the second I2S interface:
■ I2S bit clock: I2S_SCLK1 (sometimes referred to as I2S_BITCLK)
■ I2S word select: I2S_LRCK1 (sometimes referred to as I2S_WS)
■ I2S serial data out: I2S_SDATAO1
■ I2S serial data in: I2S_SDATAI1
■ I2S master clock: I2S_MCLK1
I2S_SDATAO0 and I2S_SDATAO1 are outputs.
I2S_MCLK, I2S_SCLK and I2S_LRCLK can be configured as either inputs or outputs depending on whether the master clock source
is on- or off-chip and whether the I2S is operating in Slave or Master mode.
Channel word lengths of 16 bits, 20 bits, 24 bits, and 32 bits are supported, and the data is justified so that the MSB of the left-channel
data is aligned with the MSB of the I2S bus, per the I2S specification. The MSB of each data word is transmitted one bit-clock cycle
after the I2S_LRCK transition, synchronous with the falling edge of the bit clock. Left-channel data is transmitted when I2S_LRCK is
Document Number: 002-19312 Rev. *C
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