PRELIMINARY
CYW54907
The following information pertains to Figure 9:
■ The Micro-AB receptacle connects the CYW54907 to an external host or device.
■ The Micro-AB connector ID pin is connected to the CYW54907 USB2_DSEL pin.
■ The CYW54907 GPIO_9 pin is high in order to select the USB 2.0 PHY.
■ The PPC line indicates whether the USB 2.0 host controller supports port power control.
■ The OVC line is used to indicate an overcurrent condition.
■ Standard differential signal lines D+ (DP) and D– (DM) are used for the USB 2.0 interface
5.11.2 USB 2.0 Features
The following capabilities and features apply to the CYW54907 USB 2.0 PHY:
■ Compliant with the UTMI+ level 2 specification.
■ Functions as a host or device, or OTG PHY.
■ Supports high speed (HS) at 480 Mbps, full speed (FS) at 12 Mbps, and low speed (LS) at 1.5 Mbps.
■ Integrates pull-up and pull-down terminations with resistor support (per an engineering change notice to the USB 2.0 specification).
■ Contains a calibrated 45Ω termination for HS TX/RX.
■ Uses half-duplex differential data signaling with NRZI encoding.
■ Recovers the data and clock from the data stream.
■ Integrates a 960 MHz PLL with a single-ended reference clock.
■ Supports host resume and remote wake-up.
■ Supports L1 and L2 suspend, shallow sleep, and Link-Power Management (LPM).
■ Supports legacy USB 1.1 devices through a serial interface.
■ Supports dribble bits.
■ Supports LS keep-alive packets (LS EOP).
■ Support HS keep-alive packets (HS SYNC).
■ Contains an onboard BERT for self-testing (PRBS and fixed patterns).
■ Dissipates a maximum power of 150 mW for 1-port in loop-back mode.
■ Contains an integrated 3.3V to 1.2V LDO.
■ Uses 3.3V.
5.12 SPI
CYW54907 contains 2 SPI blocks. These blocks support a fixed SPI mode (CPOL = 0, CPHA = 0) and 8-bit data read/write.
■ CPOL = 0: Clock idles at 0, and each cycle consists of a pulse of 1. The leading edge is a rising edge, and the trailing edge is a
falling edge.
■ CPHA = 0: The "out" side changes the data on the trailing edge of the preceding clock cycle, while the "in" side captures the data
on (or shortly after) the leading edge of the clock cycle.
The SPI hardware blocks support a hold time of 25ns and a maximum clock frequency of 40MHz.
If a SPI slave does not support the above mode or requires a hold time greater than 25ns, a bit banging software SPI driver should
be used. Cypress's WICED SDK provides and example of such a driver. Note that the maximum SPI frequency support by a software
SPI driver is much lower than 40 MHz.
SPI0 mentioned in Table 10 is multiplexed with GPIOs and can therefore support a bit banging based software SPI driver. SPI1 is not
multiplexed with GPIOs and cannot support a bit banging based software SPI driver.
Document Number: 002-19312 Rev. *C
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