PRELIMINARY
CYW54907
5.5 JTAG and ARM Serial Wire Debug
The CYW54907 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing
during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and character-
ization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test
points or a header on all PCB designs.
The CYW54907 also supports ARM Serial Wire Debug (SWD) for connecting a JTAG debugger directly to both ARM Cortex-R4s. For
SWD, the combination of a clock and a bidirectional signal (on a single pin) provides normal JTAG debug and test functionality. The
reduced pin-count SWD interface is a high-performance alternative to the JTAG interface.
Table 6 shows the JTAG_SEL and TAP_SEL states for test and debug function selection. Test and debug function selection is
independent of the debugging interface (JTAG or SWD) being used.
Table 6. JTAG_SEL and TAP_SEL States for Test and Debug Function Selection
JTAG_SEL State
TAP_SEL State
Test and Debug Function
0
0
1
0
1
JTAG not used.
JTAG not used.
0
1
1
Access the LV tap directly for ATE and bring-up.
Access either of the ARM Cortex-R4’s directly via either the 5-pin JTAG port or the 2-pin
SWD configuration.
Note: JTAG_SEL is exposed on a dedicated physical pin. TAP_SEL uses the GPIO_8 physical pin.
5.6 PWM
The CYW54907 provides up to six independent pulse width modulation (PWM) channels. The following features apply to the PWM
channels:
■ Each channel is a square wave generator with a programmable duty cycle.
■ Each channel generates its duty cycle by dividing down the input clock.
■ Both the high and low duration of the duty cycle can be divided down independently by a 16-bit divider register.
■ Each channel can work independently or update simultaneously.
■ Pairs of PWM outputs can be inverted for devices that need a differential output.
■ Continuous or single pulses can be generated.
■ The input clock can either be a high-speed clock from a PLL channel or a lower speed clock at the crystal frequency.
5.7 SDIO 3.0
5.7.1 SDIO 3.0—Device Mode
Description
The CYW54907 WLAN section supports SDIO version 3.0, including the new UHS-I modes:
■ DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling).
■ HS: High-speed up to 50 MHz (3.3V signaling).
■ SDR12: SDR up to 25 MHz (1.8V signaling).
■ SDR25: SDR up to 50 MHz (1.8V signaling).
Note: The CYW54907 is backward compatible with SDIO v2.0 host interfaces.
The following three functions are supported:
■ Function 0 Standard SDIO function (max. BlockSize/ByteCount = 32B)
■ Function 1 Backplane Function to access the internal SoC address space (max. BlockSize/ByteCount = 64B)
■ Function 2 WLAN Function for efficient WLAN packet transfer through DMA (max. BlockSize/ByteCount = 512B)
Document Number: 002-19312 Rev. *C
Page 18 of 95
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