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BCM54907 参数 Datasheet PDF下载

BCM54907图片预览
型号: BCM54907
PDF下载: 下载PDF文件 查看货源
内容描述: [WICED™ IEEE 802.11 a/b/g/n/ac SoC with an Embedded Applications Processor]
分类和应用:
文件页数/大小: 95 页 / 1802 K
品牌: CYPRESS [ CYPRESS ]
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PRELIMINARY  
CYW54907  
3.2 External Frequency Reference  
As an alternative to a crystal, an external precision frequency reference can be used, provided that it meets the phase noise require-  
ments listed in Table 3.  
If used, the external clock should be connected to the WRF_XTAL_XON pin through an external 1000 pF coupling capacitor, as shown  
in Figure 5. The internal clock buffer connected to this pin will be turned off when the CYW54907 goes into sleep mode. When the  
clock buffer turns on and off, there will be a small impedance variation. Power must be supplied to the WRF_XTAL_VDD1P35 pin.  
Figure 5. Recommended Circuit to Use With an External Reference Clock  
1000 pF  
Reference  
WRF_XTAL_XON  
Clock  
NC  
WRF_XTAL_XOP  
Table 3. Crystal Oscillator and External Clock—Requirements and Performance  
Crystala  
External Frequency  
Referenceb C  
Parameter  
Conditions/Notes  
Units  
MHz  
Min.  
Typ.  
Max.  
Min.  
Typ.  
Max.  
Frequency  
2.4 GHz and 5 GHz bands:  
IEEE 802.11a/b/g/n/ac operation  
37.4  
37.4  
Frequency tolerance over the Without trimming  
lifetime of the equipment,  
–20  
20  
–20  
20  
ppm  
including temperaturec  
Crystal load capacitance  
ESR  
16  
pF  
60  
Drive level  
External crystal must be able to tolerate 200  
this drive level.  
µW  
Input impedance (WRF_X-  
TAL_XON)  
Resistive  
30k  
100k  
Capacitive  
7.5  
7.5  
0.2  
pF  
V
WRF_XTAL_XON  
Input low level  
DC-coupled digital signal  
0
WRF_XTAL_XON  
Input high level  
DC-coupled digital signal  
1.0  
400  
1
1.26  
V
WRF_XTAL_XON input  
voltage (see Figure 5)  
IEEE 802.11a/b/g operation only  
1200 mVp-p  
WRF_XTAL_XON input  
voltage (see Figure 5)  
IEEE 802.11n/ac AC-coupled analog  
input  
Vp-p  
Duty cycle  
Phase noised  
37.4 MHz clock  
40  
50  
60  
%
37.4 MHz clock at 10 kHz offset  
37.4 MHz clock at 100 kHz offset  
37.4 MHz clock at 10 kHz offset  
37.4 MHz clock at 100 kHz offset  
37.4 MHz clock at 10 kHz offset  
37.4 MHz clock at 100 kHz offset  
37.4 MHz clock at 10 kHz offset  
37.4 MHz clock at 100 kHz offset  
–129 dBc/Hz  
–136 dBc/Hz  
–137 dBc/Hz  
–144 dBc/Hz  
–134 dBc/Hz  
–141 dBc/Hz  
–142 dBc/Hz  
–149 dBc/Hz  
(IEEE 802.11b/g)  
Phase noised  
(IEEE 802.11a)  
Phase noised  
(IEEE 802.11n, 2.4 GHz)  
Phase noised  
(IEEE 802.11n/ac, 5 GHz)  
Document Number: 002-19312 Rev. *C  
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