ADVANCE
CYW43570
16.4 LNLDO
Table 36. LNLDO Specifications
Specification
Notes
Min
1.3
Typ
1.35
Max
1.5
Units
Input supply voltage, Vin
Min = 1.2Vo + 0.15V = 1.35V dropout voltage
requirement must be met under maximum load.
V
Output Current
–
0.1
1.1
–
150
mA
V
Output Voltage, Vo
Programmable in 25 mV steps.
Default = 1.2V
1.2
1.275
Dropout Voltage
At maximum load
Includes line/load regulation
No load
–
–4
–
–
150
+4
–
mV
Output Voltage DC Accuracy
Quiescent current
–
%
44
970
–
μA
Max load
–
990
5
μA
Line Regulation
Load Regulation
Leakage Current
Output Noise
Vin from (Vo + 0.1V) to 1.5V, max load
–
mV/V
mV/mA
μA
Load from 1 mA to 150 mA
Power-down
–
0.02
–
0.05
10
–
@30 kHz, 60–150 mA load Co = 2.2 μF
@100 kHz, 60–150 mA load Co = 2.2 μF
–
–
60
35
nV/rt Hz
nV/rt Hz
PSRR
@ 1kHz, Input > 1.35V, Co= 2.2 μF,
Vo = 1.2V
20
–
–
dB
LDO Turn-on Time
LDO turn-on time when rest of chip is up
–
0.5a
140
2.2
180
4.7
μs
External Output Capacitor, Co
Total ESR (trace/capacitor):
5–240 mΩ
μF
External Input Capacitor
Only use an external input capacitor at the
VDD_LDO pin if it is not supplied from CBUCK
output.
–
1
2.2
μF
Total ESR (trace/capacitor): 30–200 mΩ
a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
Document Number: 002-15054 Rev. *I
Page 77 of 94
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