ADVANCE
CYW43570
16.2 2.5V LDO (BTLDO2P5)
Table 34. BTLDO2P5 Specifications
Specification
Notes
Min
3.0
Typ
3.3
Max
3.6a
Units
Input supply voltage
Min = 2.5V + 0.2V = 2.7V.
Dropout voltage requirement must be met under
maximum load for performance specifications.
V
Nominal output voltage
Default = 2.5V.
Range
–
2.5
2.5
–
–
V
V
Output voltage programmability
2.2
–5
2.8
5
Accuracy at any step (including line/load
regulation), load > 0.1 mA.
%
Dropout voltage
Output current
At maximum load.
–
–
–
200
70
mV
mA
μA
0.1
–
–
Quiescent current
No load.
8
16
Maximum load at 70 mA.
Power-down mode.
–
660
1.5
–
700
5
μA
Leakage current
Line regulation
–
A
V
in from (Vo + 0.2V) to 3.6V,
–
3.5
mV/V
maximum load.
Load regulation
PSRR
Load from 1 mA to 70 mA,
Vin = 3.6V.
–
–
–
0.3
–
mV/mA
dB
Vin ≥ Vo + 0.2V, Vo = 2.5V, Co = 2.2 μF,
20
maximum load, 100 Hz to 100 kHz.
LDO turn-on time
In-rush current
Chip already powered up.
–
–
–
–
150
250
μs
Vin = Vo + 0.15V to 3.6V, Co = 2.2 μF,
No load.
mA
External output capacitor, Co
External input capacitor
Ceramic, X5R, 0402,
0.7b
2.2
4.7
2.64
–
μF
μF
(ESR: 5–240 mΩ), ±10%, 10V
For SR_VDDBATA5V pin (shared with Bandgap) –
ceramic, X5R, 0402,
(ESR: 30–200 mΩ), ±10%, 10V.
Not needed if sharing VBAT 4.7 μF capacitor with
SR_VDDBATP5V.
a. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.5V for up to
250 seconds, cumulative duration, over the lifetime of the device are allowed.
b. The minimum value refers to the residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging.
Document Number: 002-15054 Rev. *I
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