ADVANCE
CYW43570
Table 19. Signal Descriptions (Cont.)
Ball Signal Name
Type
Description
A8
PCIE_RDN0
I/O
I/O
I/O
I/O
I/O
100Ω diff pair Rx data signal negative.
PCIE clock request signal.
PCIE preset signal.
B14
A14
A4
PCIE_CLKREQ_L
PCIE_PERST_L
PCIE_TESTP
100Ω diff pair.
A5
PCIE_TESTN
100Ω diff pair.
WLAN GPIO Interface
Note: The GPIO signals can be multiplexed via software and the JTAG_SEL pin to support other functions. See Table 17 for
additional details.
B17
A16
B4
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Programmable GPIO pins.
E14
G2
A2
B3
L22
L23
K19
K22
K20
J19
J22
H22
H19
JTAG Interface
E13
JTAG_SEL
I/O
JTAG select. This pin must be connected to ground if the JTAG
interface is not used.
Clocks
E7
LPO_IN
I
External sleep clock input (32.768 kHz).
J5
BT_CLK_REQ
O
Asserts when WLAN wants the host to turn on the reference
clock.
U23
V23
WRF_XTAL_OUT
WRF_XTAL_IN
O
I
XTAL oscillator output.
XTAL oscillator input.
Bluetooth Transceiver
N1
C2
D2
F5
H5
BT_RF
O
Bluetooth RF input/output.
SFLASH_CLK.
BT_SF_CLK
BT_SF_CS_L
BT_SF_MISO
BT_SF_MOSI
I
I/O
I/O
I/O
SFLASH_CSN.
SFLASH master input, slave output.
SFLASH master output, slave input.
Bluetooth USB Interface
B1
BT_USB_DN
I/O
I/O
USB (Host) data negative. Negative terminal of the USB trans-
ceiver.
C1
BT_USB_DP
USB (Host) data positive. Positive terminal of the USB trans-
ceiver.
Document Number: 002-15054 Rev. *I
Page 52 of 94
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