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BCM43570KFFBG 参数 Datasheet PDF下载

BCM43570KFFBG图片预览
型号: BCM43570KFFBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Single-Chip 5G WiFi IEEE 802.11ac 2×2MAC/Baseband/Radio with IntegratedBluetooth 4.1 and EDR]
分类和应用:
文件页数/大小: 93 页 / 8056 K
品牌: CYPRESS [ CYPRESS ]
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ADVANCE  
CYW43570  
12.3 Signal Descriptions  
The signal name, type, and description of each pin in the CYW43570 is listed in Table 19. The symbols shown under Type indicate  
pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up  
resistor and PD = weak internal pull-down resistor), if any.  
Table 19. Signal Descriptions  
Ball  
Signal Name  
Type  
Description  
WLAN Receive RF Signal Interface  
T1  
WRF_RFIN_2G_CORE0  
WRF_RFIN_2G_CORE1  
WRF_RFIN_5G_CORE0  
WRF_RFIN_5G_CORE1  
WRF_RFOUT_2G_CORE0  
WRF_RFOUT_2G_CORE1  
WRF_RFOUT_5G_CORE0  
WRF_RFOUT_5G_CORE1  
WRF_TSSI_A_CORE0  
I
2.4 GHz WLAN CORE0 receiver input.  
2.4 GHz WLAN CORE1 receiver input.  
5 GHz WLAN CORE0 receiver input.  
5 GHz WLAN CORE1 receiver input.  
2.4 GHz WLAN CORE0 PA output.  
2.4 GHz WLAN CORE1 PA output.  
5 GHz WLAN CORE0 PA output.  
5 GHz WLAN CORE1 PA output.  
AC11  
AC4  
AC22  
V1  
I
I
I
O
O
O
O
I
AC13  
AC2  
AC20  
W7  
5 GHz TSSI CORE0 input from an optional external power  
amplifier/power detector.  
W16  
W9  
WRF_TSSI_A_CORE1  
I
5 GHz TSSI CORE1 input from an optional external power  
amplifier/power detector.  
WRF_GPIO_OUT_CORE0  
WRF_GPIO_OUT_CORE1  
I/O  
I/O  
GPIO or 2.4 GHz TSSI CORE0 input from an optional external  
power amplifier/power detector.  
W14  
GPIO or 2.4 GHz TSSI CORE1 input from an optional external  
power amplifier/power detector.  
RF Switch Control Lines  
U19  
W19  
V19  
T19  
R23  
R19  
N19  
P19  
R22  
N23  
P22  
N22  
M23  
M19  
M22  
L19  
RF_SW_CTRL_0  
RF_SW_CTRL_1  
RF_SW_CTRL_2  
RF_SW_CTRL_3  
RF_SW_CTRL_4  
RF_SW_CTRL_5  
RF_SW_CTRL_6  
RF_SW_CTRL_7  
RF_SW_CTRL_8  
RF_SW_CTRL_9  
RF_SW_CTRL_10  
RF_SW_CTRL_11  
RF_SW_CTRL_12  
RF_SW_CTRL_13  
RF_SW_CTRL_14  
RF_SW_CTRL_15  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Programmable RF switch control lines. The control lines are  
programmable via the driver and NVRAM file.  
PCIe Interface  
A11  
A12  
A10  
A9  
PCIE_REFCLKP  
I/O  
I/O  
I/O  
I/O  
I/O  
100diff pair clock signal positive.  
100diff pair clock signal negative.  
100diff pair Tx data signal negative.  
100diff pair Tx data signal positive.  
100diff pair Rx data signal positive.  
PCIE_REFCLKN  
PCIE_TDN0  
PCIE_TDP0  
A7  
PCIE_RDP0  
Document Number: 002-15054 Rev. *I  
Page 51 of 94  
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