ADVANCE
CYW43570
12.4 WLAN/BT GPIO Signals and Strapping Options
The pins listed in Table 20 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few
milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative
function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor
that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to GND, using a
10 kΩ resistor or less.
Note: Refer to the reference board schematics for more information.
Table 20. BT GPIO Functions and Strapping Optionsa
Pin Name
BT_GPIO4
Default Function
Description
0
1: BT Serial Flash is present.
0: BT Serial Flash is absent (default).
a. Currently, Bluetooth headless is only supported with BT_Sflash onboard.
Document Number: 002-15054 Rev. *I
Page 56 of 94
CYPRESS [ CYPRESS ]
