ADVANCE
CYW43570
Figure 23. FCBGA Ball Map, 10 mm × 10 mm Array, 242 Balls (Top View, 2 of 2)
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PCIE_REFCL PCIE_PLL_A PCIE_PERST BT_UART_R
GPIO_1
SR_VLX
SR_VLX
SR_PVSS
SR_PVSS
A
B
KN
VDD1P2
_L
TS_L
PCIE_CLKRE
Q_L
SR_VDDBAT
A5V
PCIE_AVSS
PCIE_PME_L
GPIO_0
SR_VDDBAT SR_VDDBAT
P5V P5V
C
D
E
F
LDO_VDD1P LDO_VDD1P
5
5
VOUT_LDO3 VOUT_LDO3
VSSC
JTAG_SEL
GPIO_3
VSSC
PMU_AVSS WL_REG_ON
P3_B
P3_B
VOUT_3P3_S
ENSE
VOUT_3P3
VOUT_3P3
LDO_VDDBA LDO_VDDBA
G
H
J
T5V
T5V
VSSC
VSSC
VDDC
VSSC
BT_REG_ON
VSSC
VDDIO_PMU
VDDIO
GPIO_15
GPIO_12
GPIO_9
GPIO_14
VOUT_CLDO
VSSC
VDDC
VDDC
GPIO_13
GPIO_10
GPIO_7
VOUT_BTLD
O2P5
VOUT_LNLD
O
GPIO_11
K
L
RF_SW_CTR
L_15
VDDC
VDDIO_RF
GPIO_8
RF_SW_CTR
L_13
RF_SW_CTR RF_SW_CTR
L_14 L_12
M
N
P
R
T
RF_SW_CTR
L_6
RF_SW_CTR RF_SW_CTR
VDDC
VDDC
VSSC
VSSC
L_11
L_9
RF_SW_CTR
L_7
RF_SW_CTR
L_10
VDDC
VSSC
VDDC
VSSC
VSSC
VSSC
VSSC
RGND
RGND
RF_SW_CTR
L_5
RF_SW_CTR RF_SW_CTR
L_8 L_4
VSSC
VSSC
RGND
VSSC
RGND
RF_SW_CTR
L_3
RF_SW_CTR
L_0
WRF_XTAL_ WRF_XTAL_
GND1P2 OUT
U
V
W
Y
WRF_LOGE
NG_GND1P2
RF_SW_CTR
L_2
WRF_XTAL_ WRF_XTAL_I
GND1P2
RGND
RGND
RGND
RGND
N
WRF_MMD_ WRF_VCO_ WRF_GPIO_
GND1P2
WRF_TSSI_A
_CORE1
RF_SW_CTR
L_1
WRF_XTAL_ WRF_XTAL_
GND1P2 VDD1P2
RGND
GND1P2
OUT_CORE1
WRF_XTAL_ WRF_XTAL_
GND1P2
VDD1P5
WRF_BUCK_
RGND
VDD1P5_CO AA
RE1
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
RGND
AB
AC
WRF_PA2G_ WRF_PADRV WRF_PA5G_
VBAT_VDD3 _VBAT_VDD VBAT_VDD3
P3_CORE1 3P3_CORE1 P3_CORE1
WRF_RFOUT
_2G_CORE1
WRF_RFOUT
_5G_CORE1
WRF_RFIN_5
G_CORE1
RGND
RGND
RGND
RGND
RGND
RGND
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Document Number: 002-15054 Rev. *I
Page 47 of 94
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