ADVANCE
CYW43570
9. PCI Express Interface
The PCI Express (PCIe) core on the CYW43570 is a high-performance serial I/O interconnect that is protocol compliant and electrically
compatible with the PCI Express Base Specification v2.0. This core contains all the necessary blocks, including logical and electrical
functional subblocks to perform PCIe functionality and maintain high-speed links, using existing PCI system configuration software
implementations without modification.
Organization of the PCIe core is in logical layers: Transaction Layer, Data Link Layer, and Physical Layer, as shown in Figure 19. A
configuration or link management block is provided for enumerating the PCIe configuration space and supporting generation and
reception of System Management Messages by communicating with PCIe layers.
Each layer is partitioned into dedicated transmit and receive units that allow point-to-point communication between the host and
CYW43570 device. The transmit side processes outbound packets whereas the receive side processes inbound packets. Packets
are formed and generated in the Transaction and Data Link Layer for transmission onto the high-speed links and onto the receiving
device. A header is added at the beginning to indicate the packet type and any other optional fields.
Figure 19. PCI Express Layer Model
Hardware/Software
Interface
Hardware/Software
Interface
Transaction Layer
Data Link Layer
Transaction Layer
Data Link Layer
Physical Layer
Physical Layer
Logical Subblock
Logical Subblock
Electrical Subblock
Electrical Subblock
TX
RX
TX
RX
9.1 Transaction Layer Interface
The PCIe core employs a packet-based protocol to transfer data between the host and CYW43570 device, delivering new levels of
performance and features. The upper layer of the PCIe is the Transaction Layer. The Transaction layer is primarily responsible for
assembly and disassembly of transaction layer packets (TLPs). TLP structure contains header, data payload, and end-to-end CRC
(ECRC) fields, which are used to communicate transactions, such as read and write requests and other events.
A pipelined full split-transaction protocol is implemented in this layer to maximize efficient communication between devices with credit-
based flow control of TLP, which eliminates wasted link bandwidth due to retries.
9.2 Data Link Layer
The data link layer serves as an intermediate stage between the transaction layer and the physical layer. Its primary responsibility is
to provide reliable, efficient mechanism for the exchange of TLPs between two directly connected components on the link. Services
provided by the data link layer include data exchange, initialization, error detection and correction, and retry services.
The data link layer packets (DLLPs) are generated and consumed by the data link layer. DLLPs are the mechanism used to transfer
link management information between data link layers of the two directly connected components on the link, including TLP acknowl-
edgement, power management, and flow control.
Document Number: 002-15054 Rev. *I
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