ADVANCE
CYW43570
8.3 GPIO Interface
The WLAN section of the CYW43570 supports 16 GPIOs.
Upon power up and reset, these pins become tristated. Subsequently, they can be programmed to be either input or output pins via
the GPIO control register. In addition, the GPIO pins can be assigned to various other functions.
Table 17. Strapping Options PCIe
Strapping
Options
Default Chip
Internal Pulls
PAD Names FCBGA
Description
GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
Y
Y
Y
Y
Y
–
–
–
–
–
–
–
–
–
–
–
–
sprom_present/ 0
1: SPROM is present
0: SPROM is absent (default is 0)
Applicable in PCIe host mode.
GPIO_5
Y
sflash_present
0
1: SFLASH is present
0: SFLASH is absent (default is 0)
GPIO_6
GPIO_7
Y
Y
–
–
–
–
–
–
GPIO_[8:10 Y
]
strap_host_ifc_ 1
1
Together strap_host_ifc [3], [2], and [1] is used to select interfaces:
GPIO10 GPIO9 GPIO8 WLAN Host selected Bluetooth
interprets
0
1
1
PCIe (default only for B0, B1, C0
PKG_OPT1/FCBGA-PCIe) BTUART or
BTUSB (11D+11PHY) //BT tPorts stand
alone.
GPIO_11
Y
Y
Y
Y
Y
–
–
0
–
–
–
–
GPIO_12
GPIO_13
GPIO_14
GPIO_15
Default
Resource Mode Init in ALP clock mode only.
–
–
–
–
–
–
Document Number: 002-15054 Rev. *I
Page 38 of 94
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