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BCM43570KFFBG 参数 Datasheet PDF下载

BCM43570KFFBG图片预览
型号: BCM43570KFFBG
PDF下载: 下载PDF文件 查看货源
内容描述: [Single-Chip 5G WiFi IEEE 802.11ac 2×2MAC/Baseband/Radio with IntegratedBluetooth 4.1 and EDR]
分类和应用:
文件页数/大小: 93 页 / 8056 K
品牌: CYPRESS [ CYPRESS ]
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ADVANCE  
CYW43570  
7.5.1 I2S Timing  
Note: Timing values specified in Table 16 are relative to high and low threshold levels.  
Table 16. Timing for I2S Transmitters and Receivers  
Transmitter  
Receiver  
Lower Limit Upper Limit  
Min Max Min Max  
Lower LImit  
Min Max  
Ttr  
Master Mode: Clock generated by transmitter or receiver  
Upper Limit  
Min Max  
Notes  
a
Clock Period T  
Tr  
b
b
HIGH tHC  
LOWtLC  
0.35Ttr  
0.35Ttr  
0.35Ttr  
0.35Ttr  
Slave Mode: Clock accepted by transmitter or receiver  
c
c
d
HIGH tHC  
0.35Ttr  
0.35Ttr  
0.35Ttr  
0.35Ttr  
LOW tLC  
Rise time tRC  
Transmitter  
Delay tdtr  
0.15Ttr  
e
d
0
0.8T  
Hold time thtr  
Receiver  
f
f
Setup time tsr  
Hold time thr  
0.2Tr  
0
a. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer  
rate.  
b. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and  
t
LC are specified with respect to T.  
c. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So  
long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used.  
d. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can  
result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than  
or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr.  
e. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving  
the receiver sufficient setup time.  
f. The data setup and hold time must not be less than the specified receiver setup and hold time.  
Document Number: 002-15054 Rev. *I  
Page 35 of 94  
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