ADVANCE
CYW43570
Note: The time periods specified in Figure 17 and Figure 18 are defined by the transmitter speed. The receiver specifications must
match transmitter performance.
Figure 17. I2S Transmitter Timing
T
tRC
*
tLC > 0.35T
tHC > 0.35T
VH = 2.0V
VL = 0.8V
SCK
thtr > 0
totr < 0.8T
SD and WS
T = Clock period
Ttr = Minimum allowed clock period for transmitter
T = Ttr
* tRC is only relevant for transmitters in slave mode.
Figure 18. I2S Receiver Timing
T
tLC > 0.35T
tHC > 0.35
VH = 2.0V
VL = 0.8V
SCK
tsr > 0.2T
thr > 0
SD and WS
T = Clock period
Tr = Minimum allowed clock period for transmitter
T > Tr
Document Number: 002-15054 Rev. *I
Page 36 of 94
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