CYW4343X
21. Interface Timing and AC Characteristics
Note: Values in this data sheet are design goals and are subject to change based on the results of device characterization.
Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in
Table 28 on page 90 and Table 30 on page 91. Functional operation outside of these limits is not guaranteed.
21.1 SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 51 and Table 48 on page 113.
Figure 51. SDIO Bus Timing (Default Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tODLY
(max)
(min)
Document No. 002-14797 Rev. *H
Page 112 of 128
CYPRESS [ CYPRESS ]
