CYW4343X
19.4 LNLDO
Table 45. LNLDO Specifications
Notes
Specification
Min.
1.3
Typ.
1.35
Max.
1.5
Units
Input supply voltage, Vin
Min. VIN = VO + 0.15V = 1.35V
V
(where VO = 1.2V) dropout voltage requirement must be
met under maximum load.
Output current
–
0.1
1.1
–
150
mA
V
Output voltage, Vo
Programmable in 25 mV steps.
Default = 1.2V
1.2
1.275
Dropout voltage
At maximum load
Includes line/load regulation
No load
–
–
150
+4
12
mV
%
Output voltage DC accuracy
Quiescent current
–4
–
–
10
970
–
µA
Max. load
–
990
5
µA
Line regulation
Load regulation
V
in from (Vo + 0.15V) to 1.5V,
–
mV/V
200 mA load
Load from 1 mA to 200 mA:
Vin ≥ (Vo + 0.12V)
–
0.025
0.045
mV/mA
µA
Leakage current
Output noise
Power-down, junction temp. = 85°C
–
–
5
–
20
@30 kHz, 60–150 mA load Co = 2.2 µF
@100 kHz, 60–150 mA load Co = 2.2 µF
60
35
nV/ Hz
–
PSRR
@1 kHz, Vin ≥ (Vo + 0.15V), Co = 4.7 µF
20
–
–
–
dB
LDO turn-on time
LDO turn-on time when rest of chip is up
140
2.2
180
4.7
µs
0.5a
External output capacitor, Co
Total ESR (trace/capacitor):
5 mΩ–240 mΩ
µF
External input capacitor
Only use an external input capacitor at the VDD_LDO
pin if it is not supplied from CBUCK output.
Total ESR (trace/capacitor): 30 mΩ–200 mΩ
–
1
2.2
µF
a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
Document No. 002-14797 Rev. *H
Page 109 of 128
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