CYW4343X
Table 43. LDO3P3 Specifications (Cont.)
Notes
Specification
Min.
–5
Typ.
Max.
+5
Units
Output voltage DC accuracy
Quiescent current
Includes line/load regulation.
No load
–
%
–
–
66
–
85
µA
Line regulation
Vin from (Vo + 0.2V) to 4.8V, max. load
3.5
mV/V
Load regulation
PSRR
load from 1 mA to 450 mA
–
–
–
0.3
–
mV/mA
dB
Vin ≥ Vo + 0.2V,
20
Vo = 3.3V, Co = 4.7 µF,
Max. load, 100 Hz to 100 kHz
LDO turn-on time
Chip already powered up.
–
1.0b
160
4.7
250
µs
External output capacitor, Co
Ceramic, X5R, 0402,
(ESR: 5 mΩ–240 mΩ), ± 10%, 10V
5.64
µF
External input capacitor
For SR_VDDBATA5V pin (shared with band gap) –
Ceramic, X5R, 0402,
4.7
–
µF
(ESR: 30m-200 mΩ), ± 10%, 10V.
Not needed if sharing VBAT capacitor 4.7 µF with
SR_VDDBATP5V.
a. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are
allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed.
b. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
19.3 CLDO
Table 44. CLDO Specifications
Specification
Input supply voltage, Vin
Notes
Min. Typ. Max.
Units
Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement 1.3
must be met under maximum load.
1.35
1.5
V
Output current
–
0.2
–
200
mA
V
Output voltage, Vo
Programmable in 10 mV steps.
Default = 1.2.V
0.95
1.2
1.26
Dropout voltage
At max. load
–
–
150
+4
–
mV
%
Output voltage DC accuracy
Quiescent current
Includes line/load regulation
No load
–4
–
–
13
1.24
–
µA
200 mA load
–
–
mA
mV/V
Line regulation
Vin from (Vo + 0.15V) to 1.5V,
maximum load
–
5
Load regulation
Leakage current
Load from 1 mA to 300 mA
Power down
–
0.02
0.05
20
3
mV/mA
µA
–
5
1
–
Bypass mode
–
µA
PSRR
@1 kHz, Vin ≥ 1.35V, Co = 4.7 µF
20
–
dB
Start-up time of PMU
VDDIO up and steady. Time from the REG_ON rising
edge to the CLDO
–
–
–
700
180
µs
µs
reaching 1.2V.
LDO turn-on time
LDO turn-on time when rest of the
chip is up.
140
1.1a
–
External output capacitor, Co
External input capacitor
Total ESR: 5 mΩ–240 mΩ
2.2
1
–
µF
µF
Only use an external input capacitor
at the VDD_LDO pin if it is not supplied
from CBUCK output.
2.2
a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
Document No. 002-14797 Rev. *H
Page 108 of 128
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